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11.发明授权公开(公告)号：US07237219B2
公开(公告)日：2007-06-26
申请号：US11042978
申请日：2005-01-25
申请人： Hiroshi Ikeda , Takeshi Nakayama
发明人： Hiroshi Ikeda , Takeshi Nakayama
IPC分类号： G06F9/45 , G06F17/50 , H03K17/693
CPC分类号： G06F17/5068
摘要： A multilayer wiring board formed by laminating a plurality of dielectrics including a specific dielectric capable of embedding components therein is separated into first and second portions that are respectively made up of sets of dielectrics on opposite sides of the specific dielectric. A first aid unit stores design information about placement of objects to the first portion, and manages and displays the design information according to a user command to aid in design of the first portion. A second aid unit stores design information about placement of objects to the second portion, and manages and displays the design information according to a user command to aid in design of the second portion. Further, the first and second aid units each store design information about placement of boundary objects which extend to both the first and second portions, and cooperatively manage the design information and each display it.
摘要翻译： 通过层叠多个电介质而形成的多层布线基板被分离成第一和第二部分，第一和第二部分分别由比电介质的相对侧上的电介质构成。 急救单元将关于对象的放置的设计信息存储到第一部分，并且根据用户命令来管理和显示设计信息以辅助第一部分的设计。 辅助单元将关于对象的放置的设计信息存储到第二部分，并且根据用户命令来管理和显示设计信息以辅助第二部分的设计。 此外，第一辅助单元和第二辅助单元各自存储关于延伸到第一和第二部分的边界对象的放置的设计信息，并且协作地管理设计信息并且每个显示它们。
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公开(公告)号：US20060065746A1
公开(公告)日：2006-03-30
申请号：US11252584
申请日：2005-10-19
IPC分类号： G06K19/06
CPC分类号： G11C7/22 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C11/4096
摘要： A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.
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13.发明申请Device, method, and program for computer aided design of flexible substrates 审中-公开柔性基板计算机辅助设计的装置，方法和程序公开(公告)号：US20050287871A1
公开(公告)日：2005-12-29
申请号：US11156659
申请日：2005-06-21
CPC分类号： G06F17/5068 , G06F2217/40 , H05K1/0393 , H05K3/0005
摘要： A device, method, and program too facilitate the design of flexible printed circuit boards is disclosed which generates, as a prohibited space, a position assumed to be occupied by a part on an opposing printed circuit board when the printed circuit board is bent from a bend position. Design preparation of a bendable flexible printed circuit board can be efficiently checked by checking for the presence/absence of interference between parts and prohibited spaces.
摘要翻译： 一种装置，方法和程序太容易设计出柔性印刷电路板的设计，当印刷电路板从一个印刷电路板弯曲时，该柔性印刷电路板被设计为被禁止的空间，该位置被假定为由相对的印刷电路板上的一部分占据的位置 弯曲位置。 通过检查部件和禁止空间之间是否存在干扰，可以有效地检查可弯曲的柔性印刷电路板的设计准备。
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公开(公告)号：US20050156476A1
公开(公告)日：2005-07-21
申请号：US11074745
申请日：2005-03-09
IPC分类号： H02K17/16
CPC分类号： H02K17/165
摘要： A rotor conductor upper portion positioned near to an outer periphery of a rotor has a trapezoidal, cross sectional shape, a rotor conductor lower portion positioned nearer to a center of the rotor than the rotor conductor upper portion has a rectangular, cross sectional shape, and the rotor conductor upper portion has a height h1=27 mm or more in the case where rotor conductors are made of brass, and a height h1=7 mm or more in the case where the rotor conductors are made of copper.
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15.发明申请Mobile terminal, circuit board, circuit board design aiding apparatus and method, design aiding program, and storage medium having stored therein design aiding program 失效移动终端，电路板，电路板设计辅助设备和方法，设计辅助程序，以及存储在其中的存储介质设计辅助程序公开(公告)号：US20050081049A1
公开(公告)日：2005-04-14
申请号：US10959987
申请日：2004-10-08
CPC分类号： G06F21/87 , G06F17/5068 , H01L2224/16225 , H05K1/0275 , H05K1/186 , H05K3/0005 , H05K2201/10151
摘要： A circuit board is provided in which tamper resistance is improved by making probing by third parties difficult, while solving problems associated with the current techniques and manufacturing costs. A signal line through which a confidential signal requiring tamper resistance flows and components 32 and 33 connected to the signal line 21 by the terminals thereof, are laid out in a component-containing layer 13 of a circuit board 10. Only a confidential signal having been encrypted through a predetermined component 31 is outputted to an observation point 34 provided on a surface of the circuit board 10. External observation and control of the confidential signal is performed by decoding a cipher provided by the component 31 to the signal which appears at the observation point 34.
摘要翻译： 提供了一种电路板，其中通过使第三方的探测困难，同时解决与当前技术和制造成本相关的问题，提高了防篡改性。 要求篡改电阻的机密信号流过的信号线和其端子与信号线21连接的部件32和33布置在电路板10的部件含有层13中。只有机密信号已被 通过预定部件31加密的信号被输出到设置在电路板10的表面上的观察点34.机密信号的外部观察和控制是通过将由部件31提供的密码解码为在观察时出现的信号 点34。
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公开(公告)号：US06188493B1
公开(公告)日：2001-02-13
申请号：US09058242
申请日：1998-04-10
IPC分类号： H04N146
CPC分类号： H04N1/46
摘要： An electronic blackboard device capable of performing color printing. Data read by an image sensor is converted to digital data by an A/D converter and provided via a shading correcting circuit and a converter to a printer control circuit, which causes a color printer to print the appropriate data in a color corresponding to a marker.
摘要翻译： 能够进行彩色打印的电子黑板装置。 由图像传感器读取的数据由A / D转换器转换成数字数据，经由阴影校正电路和转换器提供给打印机控制电路，使得彩色打印机以对应于标记的颜色打印适当的数据 。
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17.发明授权Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor 失效电可编程和可擦除的非易失性半导体存储器件及其操作方法
公开(公告)号：US5898606A
公开(公告)日：1999-04-27
申请号：US841372
申请日：1997-04-30
申请人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
发明人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
IPC分类号： G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11517 , G11C16/0408 , G11C16/0416 , G11C16/16 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7883
摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.
摘要翻译： 在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。 因此，多个存储单元的阈值电压增加。 在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。 因此，所选存储单元的阈值电压降低。
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18.发明授权Nonvolatile semiconductor memory device and method of erasing stored data thereof 失效非易失性半导体存储器件及其存储数据的擦除方法
公开(公告)号：US5563824A
公开(公告)日：1996-10-08
申请号：US357697
申请日：1994-12-16
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A source line of a memory array included in a flash memory is set to a 3V potential by a source line circuit, a power supply voltage of 6V is applied to a sense amplifier, and 3V is applied as the ground potential. After the setting of such potential conditions, reading of the memory array is performed. When current flows to the memory cells as a result of reading, it means that the memory cell has been erased. If the current does not flows through the memory cell, erasure pulse is applied again and every memory cell is verified.
摘要翻译： 包含在闪速存储器中的存储器阵列的源极线通过源极线电路设置为3V电位，6V的电源电压被施加到读出放大器，并且施加3V作为接地电位。 在设置这样的潜在条件之后，执行存储器阵列的读取。 当电流由于读取而流向存储单元时，这意味着存储单元已被擦除。 如果电流不流过存储单元，则再次施加擦除脉冲，并且验证每个存储单元。
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19.发明授权
公开(公告)号：US5548557A
公开(公告)日：1996-08-20
申请号：US179731
申请日：1994-01-11
申请人： Tomoshi Futatsuya , Masaaki Mihara , Yasushi Terada , Takeshi Nakayama , Yoshikazu Miyawaki , Shinichi Kobayashi , Minoru Ohkawa
发明人： Tomoshi Futatsuya , Masaaki Mihara , Yasushi Terada , Takeshi Nakayama , Yoshikazu Miyawaki , Shinichi Kobayashi , Minoru Ohkawa
CPC分类号： G11C29/804 , G11C16/08 , G11C29/82 , G11C29/848
摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.
摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。
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20.发明授权Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming 失效并入数据锁存器和页模式编程的地址计数器的非易失性半导体存储器件
公开(公告)号：US5521863A
公开(公告)日：1996-05-28
申请号：US430032
申请日：1995-04-27
申请人： Shinichi Kobayashi , Takeshi Nakayama , Yoshikazu Miyawaki , Tomoshi Futatsuya , Yasushi Terada
发明人： Shinichi Kobayashi , Takeshi Nakayama , Yoshikazu Miyawaki , Tomoshi Futatsuya , Yasushi Terada
CPC分类号： G11C16/12 , G11C16/10 , G11C2216/14
摘要： A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.
摘要翻译： 消除了连接到每个位线的列锁存器和高压开关，并且新提供地址计数器和数据锁存器。 数据锁存器布置在I / O缓冲器和Y门之间。 在编程周期中，地址计数器被激活，并且连续选择Y门中的传输门。 因此，根据存储在数据锁存器中的写数据，高电压Vpp或0V周期地施加于存储单元阵列中的位线。
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