公开(公告)号：US20140281092A1

公开(公告)日：2014-09-18

申请号：US13799327

申请日：2013-03-13

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

IPC: G06F13/24

CPC classification number: G06F9/4812 ,  G06F11/0772

Abstract: Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

Abstract translation: 用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。 进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。 其他处理器核心执行从属SMI处理程序。 主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。 响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。 进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。 描述和要求保护其他实施例。

公开(公告)号：US20130332781A1

公开(公告)日：2013-12-12

申请号：US13997870

申请日：2012-06-06

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0793

Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

Abstract translation: 本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器 输入/输出错误容纳事件。 在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

公开(公告)号：US20120079306A1

公开(公告)日：2012-03-29

申请号：US12890222

申请日：2010-09-24

Applicant: Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

Inventor： Sarathy Jayakumar ,  Gopal R. Mundada ,  Palsamy Sakthikumar

IPC: G06F11/30 ,  G06F13/20

CPC classification number: G06F11/3062 ,  G06F11/3031 ,  G06F11/3037 ,  G06F11/327

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract translation: 描述系统运行时的内存重新配置。 在一个示例中，系统包括用于承载存储器板并且将存储器板连接到存储器控制器用于读取和写入操作的存储器插槽，具有多个状态寄存器以记录存储器槽的状态的逻辑设备和 多个控制寄存器来控制存储器插槽的操作，以及总线接口，通过直接信号线耦合到存储器插槽，以与存储器槽通信状态和控制信号，并通过串行总线耦合到逻辑器件以传送状态和 控制信号与逻辑器件。

公开(公告)号：US20210096848A1

公开(公告)日：2021-04-01

申请号：US17120072

申请日：2020-12-11

Applicant: Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

Inventor： Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

IPC: G06F8/656 ,  G06F9/48 ,  G06F9/4401 ,  G06F9/455 ,  G06F12/1027

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller (e.g., baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.

公开(公告)号：US20200285461A1

公开(公告)日：2020-09-10

申请号：US16841410

申请日：2020-04-06

Applicant: Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Xiaojin Yuan ,  Haiyue Wang ,  Chong Han

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Xiaojin Yuan ,  Haiyue Wang ,  Chong Han

IPC: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/445

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.

公开(公告)号：US20200174943A1

公开(公告)日：2020-06-04

申请号：US16206516

申请日：2018-11-30

Applicant: Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

IPC: G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F9/38 ,  G06F11/22

Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

公开(公告)号：US20150089287A1

公开(公告)日：2015-03-26

申请号：US14127548

申请日：2013-09-23

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Krishnakanth V. Sistla

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Krishnakanth V. Sistla

IPC: G06F11/07 ,  G06F13/24 ,  G06F11/30 ,  G06F12/08 ,  G06F11/16 ,  G06F1/30

CPC classification number: G06F11/079 ,  G06F1/30 ,  G06F11/14 ,  G06F11/1441 ,  G06F11/165 ,  G06F11/2015 ,  G06F11/3031 ,  G06F11/3072 ,  G06F12/0802 ,  G06F12/0804 ,  G06F13/24 ,  G06F2201/86

Abstract: An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system.

Abstract translation: 事件管理资源监视处理器环境。 响应于在处理器环境中检测到触发事件的发生，事件管理资源启动处理器高速缓存数据从处理器环境中的易失性存储器传送到非易失性存储器。 可以将事件管理资源配置为产生与缓存数据传送相关联的状态信息到相应的非易失性存储器资源。 事件管理资源将状态信息存储在非易失性存储资源中，供以后检索。 因此，与导致传送的事件相关联的状态信息可用于在随后的相应计算机系统的加电或重新启动时进行分析。

公开(公告)号：US08402186B2

公开(公告)日：2013-03-19

申请号：US12459423

申请日：2009-06-30

Applicant: Sarathy Jayakumar

Inventor： Sarathy Jayakumar

IPC: G06F13/42 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F9/4411

Abstract: In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，信号从基本输入/输出系统发送到设备，以指示基本输入/输出系统需要获得对共享资源的控制。 信号从设备发送到基本输入/输出系统，指示基本输入/输出系统现在可以控制共享资源。 描述和要求保护其他实施例。

公开(公告)号：US20110154104A1

公开(公告)日：2011-06-23

申请号：US12645778

申请日：2009-12-23

Applicant: Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

Inventor： Robert C. Swanson ,  Mahesh S. Natu ,  Rahul Khanna ,  Murugasamy K. Nachimuthu ,  Sarathy Jayakumar ,  Anil S. Keshavamurthy ,  Narayan Ranganathan

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/16 ,  G06F11/20 ,  G06F12/10

CPC classification number: G06F11/203 ,  G06F11/1666 ,  G06F11/20

Abstract: In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明提供了处理在高可用性系统中的存储器迁移操作期间发生的错误的能力。 此外，可以使用一种方法来将存储在存储器的非镜像存储器区域中的存储器页面动态重映射到镜像存储器区域。 该动态重新映射可以响应于确定存储器页已经被访问多于阈值次数，指示页面上的信息的关键性。 描述和要求保护其他实施例。

公开(公告)号：US20090172372A1

公开(公告)日：2009-07-02

申请号：US11967299

申请日：2007-12-31

Applicant: Mohan J. Kumar ,  Sarathy Jayakumar ,  Sham Datta

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Sham Datta

IPC: G06F9/26

CPC classification number: G06F9/4812

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract translation: 一种方法包括确定多个存储器地址，每个存储器地址彼此不同。 该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。 该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。 还公开了一种相关的机器可读介质。