公开(公告)号：US20140281356A1

公开(公告)日：2014-09-18

申请号：US14011655

申请日：2013-08-27

Applicant: NVIDIA CORPORATION

Inventor： Cameron BUSCHARDT ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  James Leroy DEMING ,  Brian FAHS

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/301

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract translation: 本发明的一个实施例包括耦合到存储器管理单元（MMU）的微控制器。 MMU耦合到包括在物理存储器中的页表，并且微控制器被配置为执行与物理存储器和页表相关联的一个或多个虚拟存储器操作。 在操作中，微控制器响应于通过虚拟存储器地址的无效存储器访问而接收由MMU产生的页面错误。 为了纠正这种页面错误，微控制器执行操作以将虚拟存储器地址映射到物理存储器中的适当位置。 相比之下，在现有技术的系统中，故障处理器通常会补救页面错误。 有利地，由于微控制器相对于MMU和物理存储器在本地执行这些任务，所以与补救页错误相关联的延迟可能会降低。 因此，整体系统性能可能会增加。

公开(公告)号：US20140281263A1

公开(公告)日：2014-09-18

申请号：US14109678

申请日：2013-12-17

Applicant: NVIDIA CORPORATION

Inventor： James Leroy DEMING ,  Jerome F. DULUK, Jr. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsay EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

Abstract translation: 本发明的一个实施例是包括一个或多个流式多处理器（SM）并且实现每SM的重放单元的并行处理单元（PPU）。 当检测到与由特定SM发出的存储器事务相关联的页面错误时，相应的重放单元使得SM，而不是任何未受影响的SM停止发行新的存储器事务。 重播单元然后将故障存储器事务和任何故障的飞行中存储器事务存储在重放缓冲器中。 当页面错误得到解决时，重播单元重播重播缓冲区中的内存事务，从重播缓冲区中移除成功的内存事务，直到所有存储的内存事务都已成功执行。 有利的是，与常规PPU相比，PPU的整体性能得到改善，在常规PPU检测到页面故障之后，停止执行包含在PPU中的所有SM的存储器事务，直到故障被解决为止。

公开(公告)号：US20140123145A1

公开(公告)日：2014-05-01

申请号：US13660763

申请日：2012-10-25

Applicant: NVIDIA CORPORATION

Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, Jr. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

IPC: G06F9/46

CPC classification number: G06F9/5027 ,  G06F12/1045 ,  G06F12/109

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US20140122829A1

公开(公告)日：2014-05-01

申请号：US13660815

申请日：2012-10-25

Applicant: NVIDIA CORPORATION

Inventor： Nick BARROW-WILLIAMS ,  Brian FAHS ,  Jerome F. DULUK, JR. ,  James Leroy DEMING ,  Timothy John PURCELL ,  Lucien DUNNING ,  Mark HAIRGROVE

IPC: G06F12/10

CPC classification number: G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Abstract translation: 一种用于同时执行多个任务的技术，每个任务具有独立的虚拟地址空间，包括为每个任务分配地址空间标识符（ASID），并且构建每个虚拟存储器访问请求以包括虚拟地址和ASID。 在虚拟到物理地址转换期间，ASID选择相应的页表，其中包括ASID和相关任务的虚拟到物理地址映射。 翻译后备缓冲区（TLB）的条目包括虚拟地址和ASID，以完成对物理地址的每个映射。 可以实现对共享虚拟地址空间的任务的深度调度，以提高对TLB和数据高速缓存的高速缓存亲和性。

公开(公告)号：US20230315328A1

公开(公告)日：2023-10-05

申请号：US17698409

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Hemayet HOSSAIN ,  Steven E. MOLNAR ,  Jonathon Stuart Ramsay EVANS ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Vyas VENKATARAMAN ,  Mark HAIRGROVE ,  Geoffrey GERFIN ,  Jeffrey M. SMITH ,  Terje BERGSTROM ,  Vikram SETHI ,  Piyush PATEL

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

公开(公告)号：US20170161206A1

公开(公告)日：2017-06-08

申请号：US15437400

申请日：2017-02-20

Applicant: NVIDIA Corporation

Inventor： James Leroy DEMING ,  Jerome F. DULUK, JR. ,  John MASHEY ,  Mark HAIRGROVE ,  Lucien DUNNING ,  Jonathon Stuart Ramsey EVANS ,  Samuel H. DUNCAN ,  Cameron BUSCHARDT ,  Brian FAHS

IPC: G06F12/1027 ,  G06F9/46

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F12/08 ,  G06F2212/301 ,  G06F2212/684

Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

公开(公告)号：US20160357482A1

公开(公告)日：2016-12-08

申请号：US15243909

申请日：2016-08-22

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  James Leroy DEMING ,  Lucien DUNNING ,  Brian FAHS ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY ,  James M. VAN DYKE

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

Abstract translation: 本发明的一个实施例提出了一种用于将存储器页从第一存储器迁移到第二存储器的计算机实现的方法。 该方法包括确定由第一存储器支持的第一页大小。 该方法还包括确定由第二存储器支持的第二页大小。 该方法还包括基于与存储器页相关联的页面状态目录中的条目来确定存储器页面的使用历史。 该方法还包括基于第一页面大小，第二页面大小和使用历史来在第一存储器和第二存储器之间迁移存储器页面。

公开(公告)号：US20150206277A1

公开(公告)日：2015-07-23

申请号：US14601223

申请日：2015-01-20

Applicant: Nvidia Corporation

Inventor： Amit RAO ,  Ashish SRIVASTAVA ,  Yogesh KINI ,  Alban DOUILLET ,  Geoffrey GERFIN ,  Mayank KAUSHIK ,  Nikita SHULGA ,  Vyas VENKATARAMAN ,  David FONTAINE ,  Mark HAIRGROVE ,  Piotr JAROSZYNSKI ,  Stephen JONES ,  Vivek KINI

IPC: G06T1/60 ,  G06F12/10 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F9/5016 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).

Abstract translation: 本发明有助于跨多个组件的统一虚拟地址的有效和有效的利用。 在一个实施例中，所提出的新方法或解决方案使用与图形处理单元（GPU）驱动程序映射相结合的中央处理单元（CPU）上的操作系统（OS）分配，以在GPU和CPU两者之间提供统一的虚拟地址（VA）。 新的方法有助于确保GPU VA指针不会与OS CPU分配提供的CPU指针相冲突（例如，像“malloc”C运行时API返回的一样）等。

公开(公告)号：US20140281358A1

公开(公告)日：2014-09-18

申请号：US14055382

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，产生第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。

公开(公告)号：US20140281357A1

公开(公告)日：2014-09-18

申请号：US14055367

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. DULUK, JR. ,  Cameron BUSCHARDT ,  Sherry CHEUNG ,  James Leroy DEMING ,  Samuel H. DUNCAN ,  Lucien DUNNING ,  Robert GEORGE ,  Arvind GOPALAKRISHNAN ,  Mark HAIRGROVE ,  Chenghuan JIA ,  John MASHEY

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract translation: 用于管理虚拟内存的系统。 该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。 该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，生成第一页错误 对应于第一虚拟存储器地址的映射。 该系统还包括与第一处理单元相关联的第一复制引擎。 第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。 第一复制引擎还被配置为更新第一页表以包括第一映射。