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公开(公告)号：US20110156005A1
公开(公告)日：2011-06-30
申请号：US12655468
申请日：2009-12-30
申请人： Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yih Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/772
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。
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公开(公告)号：US08592803B2
公开(公告)日：2013-11-26
申请号：US13442098
申请日：2012-04-09
申请人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
发明人： Ravi Pillarisetty , Been-Yin Jin , Benjamin Chu-Kung , Matthew V. Metz , Jack T. Kavalieros , Marko Radosavljevic , Roza Kotlyar , Willy Rachmady , Niloy Mukherjee , Gilbert Dewey , Robert S. Chau
IPC分类号： H01L29/06 , H01L29/778
CPC分类号： H01L27/092 , H01L21/02532 , H01L21/02546 , H01L21/283 , H01L27/088 , H01L29/0653 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66522 , H01L29/66553 , H01L29/775 , H01L29/7782
摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
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公开(公告)号：US20140103397A1
公开(公告)日：2014-04-17
申请号：US14141648
申请日：2013-12-27
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号：US20140054548A1
公开(公告)日：2014-02-27
申请号：US14069880
申请日：2013-11-01
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been-Yih Jin , Robert S. Chau
IPC分类号： H01L29/775 , H01L21/76 , H01L29/66
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
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公开(公告)号：US08575596B2
公开(公告)日：2013-11-05
申请号：US13647952
申请日：2012-10-09
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L31/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号：US08283653B2
公开(公告)日：2012-10-09
申请号：US12646477
申请日：2009-12-23
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号：US20110147711A1
公开(公告)日：2011-06-23
申请号：US12646477
申请日：2009-12-23
申请人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人： Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号： H01L29/06 , H01L21/338
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译： 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号：US09711591B2
公开(公告)日：2017-07-18
申请号：US13997607
申请日：2011-12-28
申请人： Niloy Mukherjee , Matthew V. Metz , James M. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel , Loren Chow , Peter G. Tolchinsky , Jack T. Kavalieros , Robert S. Chau
发明人： Niloy Mukherjee , Matthew V. Metz , James M. Powers , Van H. Le , Benjamin Chu-Kung , Mark R. Lemay , Marko Radosavljevic , Niti Goel , Loren Chow , Peter G. Tolchinsky , Jack T. Kavalieros , Robert S. Chau
CPC分类号： H01L29/06 , H01L21/0237 , H01L21/0245 , H01L21/02455 , H01L21/02494 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02513 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/0259 , H01L21/02617 , H01L21/02636 , H01L21/02658 , H01L21/02664
摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.
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公开(公告)号：US20140326953A1
公开(公告)日：2014-11-06
申请号：US14334636
申请日：2014-07-17
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/15 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译： 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。
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公开(公告)号：US20110147713A1
公开(公告)日：2011-06-23
申请号：US12646621
申请日：2009-12-23
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译： 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。
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