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公开(公告)号：US08284595B2
公开(公告)日：2012-10-09
申请号：US12741299
申请日：2008-10-30
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1655 , G11C11/1659 , G11C11/1673
摘要： A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line.
摘要翻译： MRAM包括：提供为沿第一方向延伸的第一和第二位线; 存储块，其包括用于存储数据的至少一个磁阻元件; 和阅读电路。 读取电路包括电连接到第一位线的第一端子和电连接到第二位线的第二端子。 第二端子具有高阻抗，防止稳态电流在读取操作时流入。 读取电路在读取操作时将读取电流从第一端子提供给第一位线。 存储块被配置为使得读取电流从第一位线流向磁阻元件，并且磁读阻元件在读取操作时连接到第二位线。 读取电路基于通过第二位线施加到第二端子的电压来控制读取电流。
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公开(公告)号：US08009467B2
公开(公告)日：2011-08-30
申请号：US12602230
申请日：2008-04-22
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C15/02 , G11C15/046
摘要： An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor. The other end of the magnetoresistance element is connected to the second word line.
摘要翻译： 根据本发明的MRAM具有：存储单元阵列; 每个连接到沿第一方向布置的一组存储器单元的第一字线和第二字线; 以矩阵形式布置的多个块; 连接到沿第一方向布置的块组的公共字线; 以及连接到沿第二方向布置的块组的位线对。 每个块具有多个存储单元，并且每个存储单元具有第一晶体管和磁阻元件。 每个块还具有多个存储单元并联连接的第二晶体管。 第二晶体管的栅极连接到公共字线。 第一晶体管的栅极连接到第一字线。 第一晶体管的源极/漏极之一连接到第一位线，而另一个连接到磁阻元件的一端，并通过第二晶体管连接到第二位线。 磁阻元件的另一端连接到第二字线。
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公开(公告)号：US20100238719A1
公开(公告)日：2010-09-23
申请号：US12741299
申请日：2008-10-30
CPC分类号： G11C11/1657 , G11C11/1655 , G11C11/1659 , G11C11/1673
摘要： A MRAM includes: first and second bit lines provided to extend in a first direction; a storage block including at least one magnetroresistive element for storing data; and a reading circuit. The reading circuit includes a first terminal electrically connected to the first bit line, and a second terminal electrically connected to the second bit line. The second terminal has a high impedance preventing a steady-state current from flowing into at a time of a reading operation. The reading circuit supplies a reading current from the first terminal to the first bit line at the time of the reading operation. The storage block is configured such that the reading current flows from the first bit line to the magnetroresistive element and the magnetroresistive element is connected to the second bit line at the time of the reading operation. The reading circuit controls the reading current on the basis of a voltage applied to the second terminal through the second bit line.
摘要翻译： MRAM包括：提供为沿第一方向延伸的第一和第二位线; 存储块，其包括用于存储数据的至少一个磁阻元件; 和阅读电路。 读取电路包括电连接到第一位线的第一端子和电连接到第二位线的第二端子。 第二端子具有高阻抗，防止稳态电流在读取操作时流入。 读取电路在读取操作时将读取电流从第一端子提供给第一位线。 存储块被配置为使得读取电流从第一位线流向磁阻元件，并且磁读阻元件在读取操作时连接到第二位线。 读取电路基于通过第二位线施加到第二端子的电压来控制读取电流。
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公开(公告)号：US20100182824A1
公开(公告)日：2010-07-22
申请号：US12602230
申请日：2008-04-22
IPC分类号： G11C11/02 , G11C11/416 , G11C8/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C15/02 , G11C15/046
摘要： An MRAM according to the present invention has: a memory cell array; a first word line and a second word line each connected to a group of memory cells arranged in a first direction; a plurality of blocks arranged in a matrix form; a common word line connected to a group of blocks arranged in the first direction; and a bit line pair connected to a group of blocks arranged in a second direction. Each block has a plurality of memory cells, and each memory cell has a first transistor and a magnetoresistance element. Each block further has a second transistor to which the plurality of memory cells are connected in parallel. A gate of the second transistor is connected to the common word line. A gate of the first transistor is connected to the first word line. One of source/drain of the first transistor is connected to the first bit line, and the other thereof is connected to one end of the magnetoresistance element and connected to the second bit line through the second transistor. The other end of the magnetoresistance element is connected to the second word line.
摘要翻译： 根据本发明的MRAM具有：存储单元阵列; 每个连接到沿第一方向布置的一组存储器单元的第一字线和第二字线; 以矩阵形式布置的多个块; 连接到沿第一方向布置的块组的公共字线; 以及连接到沿第二方向布置的块组的位线对。 每个块具有多个存储单元，并且每个存储单元具有第一晶体管和磁阻元件。 每个块还具有多个存储单元并联连接的第二晶体管。 第二晶体管的栅极连接到公共字线。 第一晶体管的栅极连接到第一字线。 第一晶体管的源极/漏极之一连接到第一位线，而另一个连接到磁阻元件的一端，并通过第二晶体管连接到第二位线。 磁阻元件的另一端连接到第二字线。
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15.发明授权Nonvolatile resistor network assembly and nonvolatile logic gate with increased fault tolerance using the same 有权非易失电阻网络组件和非易失性逻辑门，具有增加的容错能力公开(公告)号：US09100013B2
公开(公告)日：2015-08-04
申请号：US14344446
申请日：2012-09-06
IPC分类号： H03K19/00 , H03K19/173 , H03K19/177 , H03K19/18 , G11C11/16 , G11C19/08
CPC分类号： H03K19/17764 , G11C11/16 , G11C11/1675 , G11C19/0808 , H03K19/1776 , H03K19/18
摘要： Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive elements connected together; it also comprises a write means for writing into the first and second resistor networks; and writing into the first and second resistor networks is performed by the use of the write means in a manner to make total resistances of respectively the first and second resistor networks different from each other. Further provided is a nonvolatile logic gate which performs logical operation using stored data determined by the total resistances of the respective nonvolatile resistor networks.
摘要翻译： 提供了一种非易失性电阻网络组件，其特征在于：它包括第一和第二电阻器网络，每个由连接在一起的多个非易失性电阻元件组成; 它还包括写入第一和第二电阻网络的写入装置; 并且通过使用写入装置以使得第一和第二电阻网络的总电阻彼此不同的方式来执行写入第一和第二电阻器网络的写入。 还提供了一种非易失性逻辑门，其使用由各个非易失性电阻网络的总电阻确定的存储数据执行逻辑运算。
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公开(公告)号：US08902644B2
公开(公告)日：2014-12-02
申请号：US13824888
申请日：2011-12-06
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C2213/74 , G11C2213/79 , H01L43/12
摘要： A magnetoresistive element 10 having a memory cell 100 according to the present invention contains a first lower terminal n1 and a second lower terminal n2 respectively connected to both ends of a conductive layer 3 whose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors M1 respectively included in two memory cells among the plurality of memory cells 100 and adjacent to each other in a row direction (Y direction) are commonly connected to a first word line 14. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.
摘要翻译： 具有根据本发明的存储单元100的磁阻元件10包含分别连接到纵向方向不同于列方向（X方向）的导电层3的两端的第一下端子n1和第二下端子n2。 此外，分别包括在多个存储单元100中并且在行方向（Y方向）上彼此相邻的两个存储单元中的第一晶体管M1的栅极共同连接到第一字线14.结果，没有 增加单元面积，可以在单元结构的尺寸或MRMA的处理中保留余量。
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17.发明授权公开(公告)号：US08354861B2
公开(公告)日：2013-01-15
申请号：US13060574
申请日：2009-08-12
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/12 , H03K19/168 , H03K19/18
摘要： A logic gate has a magnetoresistive element, a magnetization state control unit and an output unit. The magnetoresistive element has a laminated structure having N (N is an integer not smaller than 3) magnetic layers and N−1 nonmagnetic layers that are alternately laminated. A resistance value of the magnetoresistive element varies depending on magnetization states of the N magnetic layers. The magnetization state control unit sets the respective magnetization states of the N magnetic layers depending on N input data. The output unit outputs output data that varies depending on the resistance value of the magnetoresistive element.
摘要翻译： 逻辑门具有磁阻元件，磁化状态控制单元和输出单元。 磁阻元件具有交替层叠的N（N为不小于3的整数）磁性层和N-1个非磁性层的叠层结构。 磁阻元件的电阻值根据N个磁性层的磁化状态而变化。 磁化状态控制单元根据N个输入数据来设定N个磁性层的各自的磁化状态。 输出单元输出根据磁阻元件的电阻值而变化的输出数据。
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公开(公告)号：US20110292718A1
公开(公告)日：2011-12-01
申请号：US13144480
申请日：2010-01-21
申请人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noburu Sakimura , Ryusuke Nebashi
发明人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noburu Sakimura , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , H01L43/08 , H03K19/1776 , H03K19/1778 , H03K19/18 , H03K19/20
摘要： A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要翻译： 非易失性逻辑电路包括输入部分，控制部分和输出部分。 输入部具有垂直的磁各向异性，并具有磁化状态可变的铁磁层。 控制部分包括铁磁层。 输出部分设置在输入部分和控制部分的附近，并且包括磁化状态可变的磁性隧道结元件。 基于磁化状态改变输入部的磁化状态。 输出部分的磁性隧道结元件的磁化状态基于控制部分的铁磁材料的磁化状态和输入部分的铁磁材料的磁化状态而改变。
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公开(公告)号：US09135988B2
公开(公告)日：2015-09-15
申请号：US14343325
申请日：2012-09-07
申请人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
发明人： Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada
CPC分类号： G11C11/419 , G06F9/30098 , G06F9/30101 , G06F9/4418 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C14/0081 , G11C2207/007 , H03K17/24
摘要： A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.
摘要翻译： 半导体器件包括非易失性寄存器，每个寄存器包括用于以易失性方式保存数据的保持电路和非易失性元件。 一个地址分配给每个非易失性寄存器。 非易失性寄存器控制电路执行控制，使得响应于写指令，保持在保持电路中的数据被写入具有由指令指定的地址的非易失性寄存器中的非易失性元件，并响应于 保持在非易失性元件中的数据的加载指令被保持在具有由指令指定的地址的非易失性寄存器中的保持电路中。
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公开(公告)号：US08872542B2
公开(公告)日：2014-10-28
申请号：US13825243
申请日：2011-09-21
IPC分类号： H03K19/177 , G11C13/00 , H03K19/02 , G11C29/02
CPC分类号： H03K19/17748 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0073 , H03K19/02
摘要： A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit.
摘要翻译： 一种半导体器件包括：可重构逻辑电路，包括多个电阻变化元件; 可重新配置逻辑电路的逻辑配置根据多个电阻变化元件中的每一个是处于第一电阻状态还是在电阻值低于第一电阻状态的电阻值的第二电阻状态决定; 电阻值监视电路，包括预编程到第一电阻状态的电阻变化元件; 检测预编程电阻变化元件是否保持第一电阻状态的电阻值监视电路; 以及控制器，在检测到电阻值监视电路中设置的电阻变化元件未保持第一电阻状态的情况下，将从第二电阻状态到第一电阻状态的编程中使用的电压施加到保持第一电阻状态的电阻变化元件， 设置在可重构逻辑电路中的多个电阻变化元件。
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