公开(公告)号：US07119443B2

公开(公告)日：2006-10-10

申请号：US10959634

申请日：2004-10-07

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73。 然后，通过溅射法将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，然后，将Ti膜76，Al合金膜75， 并且将TiN膜74图案化以形成第二层布线77和78。

公开(公告)号：US06853081B2

公开(公告)日：2005-02-08

申请号：US10453611

申请日：2003-06-04

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L23/48 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

公开(公告)号：US06605530B2

公开(公告)日：2003-08-12

申请号：US10287616

申请日：2002-11-05

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L214763

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

公开(公告)号：US20070148896A1

公开(公告)日：2007-06-28

申请号：US11563442

申请日：2006-11-27

申请人： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

发明人： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

IPC分类号： H01L21/20

CPC分类号： H01L28/65 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10852

摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

摘要翻译： 一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件 经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。 下部电极的底部的厚度为30nm以上。 具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

公开(公告)号：US07183170B2

公开(公告)日：2007-02-27

申请号：US10998804

申请日：2004-11-30

申请人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

发明人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

IPC分类号： H01L21/20

CPC分类号： H01L28/65 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/91

摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

摘要翻译： 在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器 以使上电极的钌膜氧化。

公开(公告)号：US20050118762A1

公开(公告)日：2005-06-02

申请号：US10998804

申请日：2004-11-30

申请人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

发明人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

IPC分类号： C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/65 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/91

摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

摘要翻译： 在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器 以使上电极的钌膜氧化。

公开(公告)号：US06479899B1

公开(公告)日：2002-11-12

申请号：US09051978

申请日：1998-04-24

申请人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

发明人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

IPC分类号： H01L2348

CPC分类号： H01L27/10808 ,  H01L27/108

摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

公开(公告)号：US06700152B2

公开(公告)日：2004-03-02

申请号：US10231053

申请日：2002-08-30

申请人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

发明人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

IPC分类号： H01L27108

CPC分类号： H01L27/10808 ,  H01L27/108

摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

摘要翻译： 存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构 公开了不增加处理次数的环境障碍措施的集成电路。 采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。 最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。 还希望电容器的平板电极覆盖芯片。

公开(公告)号：US5986299A

公开(公告)日：1999-11-16

申请号：US962730

申请日：1997-11-03

申请人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

发明人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852

摘要： A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.

摘要翻译： 本发明的半导体集成电路器件具有存储单元阵列部分和外围电路部分。 在存储单元阵列部分中，贯穿多个层间绝缘膜中的每一个并且其侧面几乎垂直的多个插头依次直接连接。 在外围电路部分中，多个插头通过用于布线的接触垫相互连接。

公开(公告)号：US06303478B1

公开(公告)日：2001-10-16

申请号：US09421125

申请日：1999-10-19

申请人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

发明人： Yoshitaka Nakamura ,  Nobuyoshi Kobayashi ,  Takuya Fukuda ,  Masayoshi Saito

IPC分类号： H01L218242

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852

摘要： A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating films are smoothed by a chemical mechanical polishing (CMP) method. The process of padding the connection holes with the metallic film is effected through a CVD or selective CVD method.

摘要翻译： 公开了一种制造具有例如存储单元阵列部分和外围电路部分的半导体器件的方法。 通过这样的方法，在半导体衬底上形成第一层间绝缘膜，通过选择性地去除第一层间绝缘膜的预定部分，第一孔的侧面基本垂直于其底部而形成第一连接孔， 通过用金属膜填充第一孔而形成第一插塞，随后在第一绝缘膜上形成第二层间绝缘膜，通过选择性地去除第二层间绝缘膜的预定部分形成第二孔， 第二孔的侧面基本上垂直于其底部，并且通过用金属膜填充第二孔而形成与第一塞直接连接的第二塞子。 在形成第一层间绝缘膜之前，在半导体衬底上形成MOS晶体管，并且形成的第一孔延伸以露出MOS晶体管的扩散层。 通过化学机械抛光（CMP）方法使第一和第二层间绝缘膜的表面平滑。 用金属膜填充连接孔的过程通过CVD或选择性CVD方法进行。