公开(公告)号：US07178046B2

公开(公告)日：2007-02-13

申请号：US11095685

申请日：2005-04-01

Applicant: Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

Inventor： Tetsuya Yamada ,  Tomoichi Hayashi ,  Sadaki Nakano ,  Takanobu Tsunoda ,  Osamu Nishii

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3287 ,  G06F8/4432 ,  G06F9/30083 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3877 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/41

Abstract: A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.

Abstract translation: 微处理器包括第一高速缓冲存储器，第一指令提取单元，第一指令解码器，第一处理单元和保存从第一指令译码器输出的控制信号的第一锁存器。 当第一指令提取单元接收到由第一处理单元执行的第一指令时，它向第一指令解码器输出第一指令。 当第一指令提取单元接收到不由第一处理单元执行的第二指令时，它向第一指令解码器输出特定指令，之后向其他锁存电路提供时钟脉冲在第一处理单元中基于暂停 对控制信号。

公开(公告)号：US06697908B2

公开(公告)日：2004-02-24

申请号：US09987145

申请日：2001-11-13

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F1200

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract translation: 主存储装置是具有多个存储体的同步动态存储器和用于确定操作模式的模式寄存器，主存储控制器耦合到处理器和主存储装置，以及用于实现对并行访问的控制的装置 在主存储控制器中布置有多个存储器组以及将操作模式设置到内置寄存器的控制。 因此，可以确保使用高通用性和常规存储器的常规处理器。

公开(公告)号：US6092172A

公开(公告)日：2000-07-18

申请号：US950668

申请日：1997-10-15

Applicant: Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

Inventor： Junichi Nishimoto ,  Osamu Nishii ,  Fumio Arakawa ,  Susumu Narita ,  Masayuki Ito ,  Makoto Toda ,  Kunio Uchiyama

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/1027 ,  G06F2212/652

Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Abstract translation: 公开了一种提高地址转换操作速度的数据处理器。 翻译后备缓冲区被分为用于数据的缓冲器和用于指令的缓冲器，用于指令的地址转换信息也被存储到用于数据的翻译后备缓冲器中，并且当用于指令的翻译后备缓冲器中发生翻译错误时，新的地址转换 从数据的翻译后备缓冲区中提取信息。 与每次在用于指令的翻译后备缓冲器中发生翻译缺口时从外部地址转换表获得地址转换信息的情况相比，可以实现地址转换操作的高速度。

公开(公告)号：US6012139A

公开(公告)日：2000-01-04

申请号：US594750

申请日：1996-01-31

Applicant: Prasenjit Biswas ,  Shumpei Kawasaki ,  Norio Nakagawa ,  Osamu Nishii ,  Kunio Uchiyama

Inventor： Prasenjit Biswas ,  Shumpei Kawasaki ,  Norio Nakagawa ,  Osamu Nishii ,  Kunio Uchiyama

IPC: G06F7/00 ,  G06F7/487 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38

CPC classification number: G06F9/30014 ,  G06F9/30167 ,  G06F9/3867 ,  G06F9/3877

Abstract: A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.

Abstract translation: 具有16位固定长度指令集的浮点单元（FPU），用于32位数据。 FPU作为RISC微处理器的一部分运行。 CPU执行所有内存寻址。 此外，通过通信寄存器传送CPU和FPU之间的数据。 FPU流水线与CPU流水线同步。 16位固定长度指令组具有用于立即加载浮点零点和/或浮点数指令的特殊指令。 为此目的有两个指示。 此外，FPU的16位固定长度指令组将非规格化数字刷新为零。 指令集也将浮点数转换为零。 指令集的FMAC指令具有累积到不同寄存器中以进行连续FMAC操作的能力。

公开(公告)号：US5267198A

公开(公告)日：1993-11-30

申请号：US953747

申请日：1992-09-29

Applicant: Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

Inventor： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC: G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC classification number: G11C7/065

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract translation: 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US20110314213A1

公开(公告)日：2011-12-22

申请号：US13008189

申请日：2011-01-18

Applicant: Kunio UCHIYAMA ,  Osamu Nishii

Inventor： Kunio UCHIYAMA ,  Osamu Nishii

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

Abstract translation: 一种处理器系统，包括：具有处理器核心和控制器核心的处理器; 以及多个同步存储器芯片，其中所述处理器和所述多个同步存储器芯片经由外部总线连接; 其中所述处理器核心和所述控制器核心经由内部总线连接; 其中所述多个同步存储器芯片根据时钟信号被操作; 其中所述控制器核心包括通过来自所述处理器核心的地址信号选择的模式寄存器，并且通过来自所述处理器核心的数据信号写入信息以选择所述多个同步存储器芯片的操作模式;以及控制单元， 基于写在模式寄存器中的信息，向多个同步存储器芯片操作模式，其中控制器核心基于写入模式寄存器中的信息或从处理器核心到多个存储器芯片的访问地址信号输出模式设置信号 选择性地通过外部总线的同步存储器芯片; 并且其中所述时钟信号被共同地提供给所述多个同步存储器芯片。

公开(公告)号：US20110208983A1

公开(公告)日：2011-08-25

申请号：US13101678

申请日：2011-05-05

Applicant: Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

Inventor： Yonetaro TOTSUKA ,  Koichiro ISHIBASHI ,  Hiroyuki MIZUNO ,  Osamu Nishii ,  Kunio UCHIYAMA ,  Takanori SHIMURA ,  Asako SEKINE ,  Yoichi KATSUKI ,  Susumu NARITA

IPC: G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US07254082B2

公开(公告)日：2007-08-07

申请号：US11363060

申请日：2006-02-28

Applicant: Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

Inventor： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC: G11C8/00 ,  G11C5/14

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Abstract translation: 相反，当通过电源开关减小不使用状态下的电路块的漏电流时，短时间内开关频繁的接通/断开操作会引起消耗功率的增加。 由于开关的接通需要预热时间，直到电路块变得可用，所以在操作期间的开关的控制使半导体器件的处理时间变差。 该开关通过CPU核心的任务持续时间进行ON / OFF控制，用于将逻辑电路和存储器核心作为一个单元进行控制。 关闭开关后，考虑到预热时间，开关将在任务结束前再次打开。

公开(公告)号：US06654305B2

公开(公告)日：2003-11-25

申请号：US10259777

申请日：2002-09-30

Applicant: Takanobu Tsunoda ,  Osamu Nishii

Inventor： Takanobu Tsunoda ,  Osamu Nishii

IPC: G11C700

CPC classification number: G11C5/146

Abstract: A system LSI including substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system LSI, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substrate-bias control-value storage unit for storing control values to be supplied to the substrate-bias generation circuits. The control values stored in the substrate-bias control-value storage unit are set by carrying out a predetermined operation. As a result, it is possible to provide a device for implementing both a high-speed operation and low power consumption without lowering the yield and for finely controlling the power consumption during the operation.

Abstract translation: 一种系统LSI，包括用于将集成在系统LSI中的功能模块彼此独立地提供衬底偏压的衬底偏置生成电路，用于控制衬底偏置生成电路的衬底偏置控制电路和衬底偏置控制值存储单元 用于存储要提供给衬底偏置发生电路的控制值。 通过执行预定的操作来设定存储在基板偏置控制值存储单元中的控制值。 结果，可以提供一种用于实现高速操作和低功耗的装置，而不降低产量并精细地控制操作期间的功率消耗。

公开(公告)号：US06604202B1

公开(公告)日：2003-08-05

申请号：US09442148

申请日：1999-11-18

Applicant: Osamu Nishii ,  Masayuki Miyazaki ,  Kiyoo Itoh

Inventor： Osamu Nishii ,  Masayuki Miyazaki ,  Kiyoo Itoh

IPC: G06F132

CPC classification number: G06F9/3885 ,  G06F9/30145 ,  G06F9/38

Abstract: In order to save a sub-threshold leak current during operation of processor, a decision circuit (instruction decoder) inputs an instruction signal and outputs an operation mode signal regarding the level of a leak current based on information about use of the circuit block. Thereby, a sub-threshold leak current in the circuit block not used can be saved.

Abstract translation: 为了在处理器的操作期间保存次阈值泄漏电流，判定电路（指令译码器）根据关于电路块的使用的信息输入指令信号并输出​​关于泄漏电流电平的操作模式信号。 因此，可以节省未使用的电路块中的次阈值泄漏电流。