公开(公告)号：US09740621B2

公开(公告)日：2017-08-22

申请号：US14716108

申请日：2015-05-19

Applicant: QUALCOMM Incorporated

Inventor： Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan ,  Colin Beaton Verrilli

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0875 ,  G06F12/0862 ,  G06F12/02 ,  G06F12/1009 ,  H03M7/30

CPC classification number: G06F12/0875 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/251 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/602 ,  H03M7/30 ,  Y02D10/13

Abstract: Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods are disclosed. In certain aspects, memory controllers are employed that can provide memory capacity compression. In certain aspects disclosed herein, a next read address prefetching scheme can be used by a memory controller to speculatively prefetch data from system memory at another address beyond the currently accessed address. Thus, when memory data is addressed in the compressed memory, if the next read address is stored in metadata associated with the memory block at the accessed address, the memory data at the next read address can be prefetched by the memory controller to be available in case a subsequent read operation issued by a central processing unit (CPU) has been prefetched by the memory controller.

公开(公告)号：US12155402B2

公开(公告)日：2024-11-26

申请号：US17997619

申请日：2021-05-07

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Natarajan Vaidhyanathan

IPC: H03M7/00 ,  G06F16/22 ,  G06N3/0495 ,  G06N3/08 ,  H03M7/30

Abstract: Techniques and apparatuses to decompress data that has been stack compressed is described. Stack compression refers to compression of data in one or more dimensions. For uncompressed data blocks that are very sparse, i.e., data blocks that contain many zeros, stack compression can be effective. In stack compression, uncompressed data block is compressed into compressed data block by removing one or more zero words from the uncompressed data block. A map metadata that maps the zero words of the uncompressed data block is generated during compression. With the use of the map metadata, the compressed data block can be decompressed to restore the uncompressed data block.

公开(公告)号：US11961007B2

公开(公告)日：2024-04-16

申请号：US16783047

申请日：2020-02-05

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Rashid Ahmed Akbar Attar ,  Raghavendar Bhavansikar

IPC: G06N3/10 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N5/04

CPC classification number: G06N3/10 ,  G06N3/045 ,  G06N3/08 ,  G06N5/04 ,  G06N3/044 ,  G06N3/063

Abstract: A method for accelerating machine learning on a computing device is described. The method includes hosting a neural network in a first inference accelerator and a second inference accelerator. The neural network split between the first inference accelerator and the second inference accelerator. The method also includes routing intermediate inference request results directly between the first inference accelerator and the second inference accelerator. The method further includes generating a final inference request result from the intermediate inference request results.

公开(公告)号：US11449125B1

公开(公告)日：2022-09-20

申请号：US17220603

申请日：2021-04-01

Applicant: QUALCOMM INCORPORATED

Inventor： Colin Beaton Verrilli ,  Matthew Severson

IPC: G06F1/00 ,  G06F1/3287 ,  G01R21/133 ,  G06F1/3296 ,  G06F1/324

Abstract: In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.

公开(公告)号：US10725740B2

公开(公告)日：2020-07-28

申请号：US16118162

申请日：2018-08-30

Applicant: QUALCOMM Incorporated

Inventor： Mattheus Cornelis Antonius Adrianus Heddes ,  Robert Dreyer ,  Colin Beaton Verrilli ,  Natarajan Vaidhyanathan ,  Koustav Bhattacharya

IPC: G06F7/544 ,  G06F15/80 ,  G06F17/16 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Providing efficient multiplication of sparse matrices in matrix-processor-based devices is disclosed herein. In one aspect, a matrix processor of a matrix-processor-based device includes a plurality of sequencers coupled to a plurality of multiply/accumulate (MAC) units for performing multiplication and accumulation operations. Each sequencer determines whether a product of an element of a first input matrix to be multiplied with an element of a second input matrix has a value of zero (e.g., by determining whether the element of the first input matrix has a value of zero, or by determining whether either the element of the first input matrix or that of the second input matrix has a value of zero). If the product of the elements of the first input matrix and the second input matrix does not have a value of zero, the sequencer provides the elements to a MAC unit to perform a multiplication and accumulation operation.

公开(公告)号：US10236917B2

公开(公告)日：2019-03-19

申请号：US15266723

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Natarajan Vaidhyanathan ,  Luther James Blackwood ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Michael Raymond Trombley ,  Colin Beaton Verrilli

IPC: H03M13/00 ,  G11C29/52 ,  G06F3/06 ,  H03M7/30 ,  G06F11/10

Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.

公开(公告)号：US10191850B2

公开(公告)日：2019-01-29

申请号：US15086817

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/08 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/04 ,  G06F12/084 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/0862

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US10152261B2

公开(公告)日：2018-12-11

申请号：US15718515

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0875 ,  H03M7/30 ,  H03M13/00 ,  G06F12/0862 ,  G06F12/12

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides multiple CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller receives a memory write request comprising write data, determines a compression pattern for the write data, and generates a CI for the write data based on the compression pattern. The compressed memory controller writes the write data to the memory line, and writes the generated CI into one or more ECC bits of the memory line. In parallel, the compressed memory controller determines whether the physical address corresponds to a CI hint directory entry, and, if so, a CI hint of the CI hint directory entry corresponding to the physical address is updated based on the generated CI.

公开(公告)号：US20180074949A1

公开(公告)日：2018-03-15

申请号：US15266765

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/502 ,  G06F2212/608 ,  Y02D10/13

Abstract: Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems is disclosed. In one aspect, a compressed memory controller (CMC) is configured to implement two compression mechanisms: a first compression mechanism for compressing small amounts of data (e.g., a single memory line), and a second compression mechanism for compressing large amounts of data (e.g., multiple associated memory lines). When performing a memory write operation using write data that includes multiple associated memory lines, the CMC compresses each of the memory lines separately using the first compression mechanism, and also compresses the memory lines together using the second compression mechanism. If the result of the second compression is smaller than the result of the first compression, the CMC stores the second compression result in the system memory. Otherwise, the first compression result is stored.

公开(公告)号：US20180074893A1

公开(公告)日：2018-03-15

申请号：US15266723

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Natarajan Vaidhyanathan ,  Luther James Blackwood ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Michael Raymond Trombley ,  Colin Beaton Verrilli

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  H03M13/00

CPC classification number: H03M13/6312 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1012 ,  G11C29/52 ,  G11C2207/102 ,  H03M7/6041

Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.