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    SCALABLE LAYOUT ARCHITECTURE FOR METAL-PROGRAMMABLE VOLTAGE LEVEL SHIFTER CELLS
    11.
    发明申请
    SCALABLE LAYOUT ARCHITECTURE FOR METAL-PROGRAMMABLE VOLTAGE LEVEL SHIFTER CELLS 审中-公开
    适用于金属可编程电压电平变换器的可分级布局架构

    公开(公告)号：US20150109045A1

    公开(公告)日：2015-04-23

    申请号：US14059361

    申请日：2013-10-21

    Applicant: QUALCOMM Incorporated

    Inventor： Ramaprasath Vilangudipitchai ,  Ohsang Kwon ,  Srivatsan Thiruvengadam

    IPC: H03K19/0185

    CPC classification number: H03K19/018585 ,  H03K19/018528

    Abstract: A layout architecture for voltage level shifters is provided. The architecture includes features of voltage level shifter cells and arrangements of the voltage level shifter cells within integrated circuits. The architecture can be used, for example, in CMOS system-on-a-chip integrated circuits implemented using metal-programmable standard cells. The architecture is also scalable for interfaces having different numbers of signals. The architecture can provide reduced area and improved performance.

    Abstract translation: 提供了电压电平转换器的布局架构。 该架构包括电压电平移位器单元的特征和集成电路内的电压电平移位器单元的布置。 该架构可以用于例如使用金属可编程标准单元实现的CMOS片上集成电路。 该架构对于具有不同数量信号的接口也是可扩展的。 该架构可以提供面积缩小和性能提升。

    LOW LEAKAGE RETENTION REGISTER TRAY
    13.
    发明申请
    LOW LEAKAGE RETENTION REGISTER TRAY 有权
    低漏电保持寄存器托盘

    公开(公告)号：US20140253197A1

    公开(公告)日：2014-09-11

    申请号：US13787666

    申请日：2013-03-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ramaprasath Vilangudipitchai ,  Prayag Bhanubhai Patel

    IPC: H03K3/012 ,  H03K3/57

    CPC classification number: H03K3/012 ,  G06F1/32 ,  H03K3/57 ,  H03K19/0016

    Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

    Abstract translation: 一种特定的方法包括接收保持信号。 响应于接收到保持信号，该方法包括将状态信息保留在保持寄存器的非易失性级中，并将功率降低到保持寄存器的易失性级。 非易失性级可以由外部电压源供电。 挥发级可由内部电压源供电。

    Clock Glitch Prevention for Retention Operational Mode
    15.
    发明申请
    Clock Glitch Prevention for Retention Operational Mode 审中-公开

    公开(公告)号：US20180224921A1

    公开(公告)日：2018-08-09

    申请号：US15425980

    申请日：2017-02-06

    Applicant: QUALCOMM Incorporated

    Inventor： Harshat Pant ,  Ramaprasath Vilangudipitchai ,  Srijith Nair ,  Mohammad Tamjidi

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/10 ,  G06F1/3296 ,  H03K5/13 ,  Y02D10/171

    Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

    Integrated circuit power rail multiplexing
    18.
    发明授权
    Integrated circuit power rail multiplexing 有权

    公开(公告)号：US09654101B2

    公开(公告)日：2017-05-16

    申请号：US14814409

    申请日：2015-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

    IPC: H03K17/693 ,  H03K19/00

    CPC classification number: H03K17/693 ,  H03K19/0016

    Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

    Latch-based Array with Robust Design-for-Test (DFT) Features
    19.
    发明申请
    Latch-based Array with Robust Design-for-Test (DFT) Features 有权
    具有鲁棒设计测试（DFT）功能的基于锁存器的阵列

    公开(公告)号：US20140226395A1

    公开(公告)日：2014-08-14

    申请号：US13767788

    申请日：2013-02-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ramaprasath Vilangudipitchai ,  Gaurav Bhargava ,  Ohsang Kwon

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G11C2207/007

    Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

    Abstract translation: 基于锁存器的存储器包括以行和列排列的多个从锁存器。 每列从锁存器从相应的主锁存器接收锁存的数据信号。 每行包括时钟门控电路和相应的复位电路。 如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。 相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。 当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。

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