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    Latching circuit
    11.
    发明授权
    Latching circuit 有权
    闭锁电路

    公开(公告)号：US08717811B2

    公开(公告)日：2014-05-06

    申请号：US13785338

    申请日：2013-03-05

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

    Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.

    Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过基于电阻的存储元件的电流。

    FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS
    12.
    发明申请
    FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS 有权
    具有包括磁性隧道结的顶部和底部电极的装置的制造和集成

    公开(公告)号：US20130244345A1

    公开(公告)日：2013-09-19

    申请号：US13887492

    申请日：2013-05-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xia Li ,  Seung H. Kang

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/222 ,  H01L43/08

    Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

    Abstract translation: 电子器件制造工艺包括沉积底部电极层。 然后在底部电极层上制造电子器件。 底部电极层的图案化是在制造电子器件之后并且在单独的工艺中对图案化顶部电极进行的。 然后在电子器件上沉积第一电介质层，然后在底部电极层上沉积第一电介质层，然后是顶部电极层。 然后在与底部电极分离的工艺中对顶部电极进行图案化。 单独图案化顶部和底部电极通过减少电子器件之间的电介质材料中的空隙来提高产率。 一种电子设备，其制造工艺非常适用于磁隧道结（MTJ）。

    Physically unclonable function based on the random logical state of magnetoresistive random-access memory
    17.
    发明授权
    Physically unclonable function based on the random logical state of magnetoresistive random-access memory 有权
    基于磁阻随机存取存储器的随机逻辑状态的物理不可克隆功能

    公开(公告)号：US09214214B2

    公开(公告)日：2015-12-15

    申请号：US14072634

    申请日：2013-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

    IPC: G11C11/16 ,  H04L9/30 ,  H04L9/32

    CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

    Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

    Abstract translation: 一个特征涉及实现物理不可克隆功能（PUF）的方法。 该方法包括将磁阻随机存取存储器（MRAM）阵列阵列暴露于正交外部磁场。 MRAM单元各自被配置为表示第一逻辑状态和第二逻辑状态之一，并且正交外部磁场定向为与MRAM单元的自由层的容易轴正交的方向，以将MRAM单元置于 不是第一逻辑状态或第二逻辑状态的中性逻辑状态。 该方法还包括去除正交的外部磁场，将阵列的每个MRAM单元随机地置于第一逻辑状态或第二逻辑状态中。

    Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)
    18.
    发明授权
    Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM) 有权
    降低自旋转矩磁阻随机存取存储器（STT-MRAM）中的源负载效应

    公开(公告)号：US09105340B2

    公开(公告)日：2015-08-11

    申请号：US14027503

    申请日：2013-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Kangho Lee ,  Seung H. Kang ,  Xiachun Zhu

    IPC: G11C11/00 ,  G11C11/16 ,  H01L43/02

    CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

    Abstract: A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

    Abstract translation: 存储单元包括磁隧道结（MTJ）结构，其包括耦合到位线和固定层的自由层。 自由层的磁矩基本上平行于处于第一状态的被钉扎层的磁矩，并且在第二状态下基本上与销钉层的磁矩反平行。 固定层具有物理尺寸以产生对应于MTJ结构的第一开关电流的偏移磁场，以便当第一电压从位线施加到耦合到第一状态的源极线时，能够在第一状态和第二状态之间切换 存取晶体管和第二开关电流，以便当第一电压从源极线施加到位线时，能够在第二状态和第一状态之间切换。

    MRAM self-repair with BIST logic
    19.
    发明授权
    MRAM self-repair with BIST logic 有权
    MRAM自修复BIST逻辑

    公开(公告)号：US08929167B2

    公开(公告)日：2015-01-06

    申请号：US13756136

    申请日：2013-01-31

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Xia Li ,  Seung H. Kang

    IPC: G11C29/00 ,  G11C11/00 ,  G11C7/10 ,  G11C29/44 ,  G11C11/16 ,  G11C11/15 ,  G11C11/155 ,  G11C29/12

    CPC classification number: G11C29/4401 ,  G11C11/15 ,  G11C11/155 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1675 ,  G11C29/12 ,  G11C2029/1208 ,  G11C2029/4402

    Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.

    Abstract translation: 存储器自修复电路包括芯片上的存储单元阵列，以及耦合到存储单元阵列的芯片上的内置自测试（BIST）电路。 BIST电路被配置为执行磁随机存取存储器（MRAM）写入操作，以将存储器单元阵列中的故障存储器单元的地址写入存储器单元阵列中的故障地址扇区。 存储器自修复电路还包括耦合在BIST电路和存储单元阵列之间的第一选择电路。 第一选择电路被配置为选择性地将BIST电路的输出和输入耦合到存储单元阵列。

    SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL
    20.
    发明申请
    SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL 有权
    编程存储器单元的系统和方法

    公开(公告)号：US20140219015A1

    公开(公告)日：2014-08-07

    申请号：US13759310

    申请日：2013-02-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

    IPC: G11C7/00 ,  G11C11/40

    CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

    Abstract: A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage.

    Abstract translation: 一种方法包括在包括重叠区域和沟道区域的半导体晶体管结构下产生击穿条件。 通过使半导体晶体管结构的栅极和重叠区域之间的第一电压差超过半导体晶体管结构的击穿电压，同时保持栅极和沟道区域之间的第二电压差小于 击穿电压。

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