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    Variable thickness gate oxide transcap
    11.
    发明授权
    Variable thickness gate oxide transcap 有权

    公开(公告)号：US10580908B2

    公开(公告)日：2020-03-03

    申请号：US15947667

    申请日：2018-04-06

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

    IPC: H01L29/93 ,  H01L27/08 ,  H01L29/06 ,  H01G7/06 ,  H01L29/739 ,  H01L29/94

    Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

    Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for row and column, transpose access operations
    13.
    发明授权
    Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for row and column, transpose access operations 有权

    公开(公告)号：US10283190B1

    公开(公告)日：2019-05-07

    申请号：US15845722

    申请日：2017-12-18

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li

    IPC: G11C7/10 ,  G11C11/22 ,  G11C11/4097 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4099

    Abstract: Transpose non-volatile (NV) memory (NVM) bit cells and related data arrays configured for both memory row and column, transpose access operations. A plurality of transpose NVM bit cells can be arranged in memory rows and columns in a transpose NVM data array. To facilitate a row read operation, the transpose NVM bit cell includes a first access transistor coupled to a word line. An activation voltage is applied to the word line to activate the first access transistor to read a memory state stored in the NVM cell circuit in a row read operation. To facilitate a column, transpose read operation, the transpose NVM bit cell includes a second access transistor coupled to a transpose word line. An activation voltage is applied to the transpose word line to activate the second access transistor to read the memory state stored in the NVM cell circuit in a column, transpose read operation.

    TRANSPOSE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS CONFIGURED FOR HORIZONTAL AND VERTICAL READ OPERATIONS
    14.
    发明申请
    TRANSPOSE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS CONFIGURED FOR HORIZONTAL AND VERTICAL READ OPERATIONS 审中-公开

    公开(公告)号：US20190096475A1

    公开(公告)日：2019-03-28

    申请号：US15712257

    申请日：2017-09-22

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Yandong Gao

    IPC: G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C7/1006 ,  G11C8/16 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

    Abstract: Transpose static random access memory (SRAM) bit cells configured for horizontal and vertical read operations are disclosed. In one aspect, a transpose SRAM bit cell includes cross-coupled inverters and horizontal and vertical read access transistors. A word line in first metal layer having an axis in a first direction is electrically coupled to a gate node of the horizontal read access transistor, and a bit line in second metal layer having an axis disposed in a second direction substantially orthogonal to the first direction is electrically coupled to the horizontal read access transistor. A transpose word line in third metal layer having an axis disposed in the second direction is electrically coupled to a gate node of the vertical read access transistor, and a transpose bit line in fourth metal layer having an axis disposed in the first direction is electrically coupled to the vertical read access transistor.

    DYNAMICALLY CONTROLLING VOLTAGE FOR ACCESS OPERATIONS TO MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) BIT CELLS TO ACCOUNT FOR AMBIENT TEMPERATURE
    15.
    发明申请
    DYNAMICALLY CONTROLLING VOLTAGE FOR ACCESS OPERATIONS TO MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) BIT CELLS TO ACCOUNT FOR AMBIENT TEMPERATURE 审中-公开

    公开(公告)号：US20190051341A1

    公开(公告)日：2019-02-14

    申请号：US15676957

    申请日：2017-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

    IPC: G11C11/16

    Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

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