公开(公告)号：US20200020686A1

公开(公告)日：2020-01-16

申请号：US16035387

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Yan WANG ,  Jie DENG ,  Giridhar NALLAPATI

IPC: H01L27/08 ,  H01L29/94 ,  H01L29/66 ,  H01L49/02 ,  H01L23/522

Abstract: An integrated circuit (e.g., a stacked capacitor) achieves higher capacitor density without additional area consumption. The integrated circuit includes a metal-oxide-semiconductor capacitor (MOSCAP), a metal-oxide-metal capacitor (MOMCAP) and a metal-insulator-metal capacitor (MIMCAP) stacked together. The MOSCAP includes a gate and source/drain (S/D) regions. The MOMCAP is included in back-end-of-line (BEOL) layers over the MOSCAP or supported by the MOSCAP.

公开(公告)号：US20190206984A1

公开(公告)日：2019-07-04

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun CHEN ,  Yangyang SUN ,  Stanley Seungchul SONG ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US20140367760A1

公开(公告)日：2014-12-18

申请号：US13974135

申请日：2013-08-23

Applicant: Qualcomm Incorporated

Inventor： Benjamin John BOWERS ,  James W. HAYWARD ,  Charanya GOPAL ,  Gregory Christopher BURDA ,  Robert J. BUCKI ,  Chock H. GAN ,  Giridhar NALLAPATI ,  Matthew D. YOUNGBLOOD ,  William R. FLEDERBACH

IPC: H01L27/02 ,  H01L21/22 ,  G06F17/50 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/22 ,  H01L27/092 ,  H01L27/11521 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/66825 ,  Y02P90/265

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract translation: 用于设计集成电路的单元库，该库包括连续扩散兼容（CDC）单元。 CDC单元包括电连接到电源轨的p掺杂扩散区，并且连接于CDC单元的左边缘到右边缘; 第一多晶硅栅极，设置在p掺杂扩散区上方并电连接到p掺杂扩散区; 电连接到接地导轨并从左边缘到右边缘连续的n掺杂扩散区域; 第二多晶硅栅极，其设置在所述n掺杂扩散区域上方并电连接到所述n掺杂扩散区域; 设置在p掺杂和n掺杂扩散区上并靠近左边缘的左浮动多晶硅栅极; 以及设置在p掺杂和n掺杂扩散区域上并且靠近右边缘的右浮动多晶硅栅极。

公开(公告)号：US20250096139A1

公开(公告)日：2025-03-20

申请号：US18468366

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed are devices that may incorporate airgaps in top signal layers and/or power layers on a frontside of a substrate. Alternatively, or in addition thereto, airgaps may also be incorporated in signal layers and/or power layers on a backside of the substrate. In this way, metal capacitances of the devices may be reduced, which thereby improves performance of semiconductor circuits such as CPUs.

公开(公告)号：US20250015047A1

公开(公告)日：2025-01-09

申请号：US18348777

申请日：2023-07-07

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Jihong CHOI ,  Giridhar NALLAPATI ,  Sivakumar KUMARASAMY ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

Abstract: An integrated circuit (IC) is described. The IC includes a first die having a first semiconductor layer, a first active device layer and a first back-end-of-line (BEOL) layer. The IC also includes a second die having a second semiconductor layer, a second active device layer and a second back-end-of-line (BEOL) layer, and on the first die. The IC further includes a through substrate via (TSV) extending through the first die and the second die.

公开(公告)号：US20240204109A1

公开(公告)日：2024-06-20

申请号：US18068992

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0673

Abstract: Disclosed are complementary field effect transistors (CFETs) with balanced n and p drive current, and methods for making the same. In an aspect, a CFET structure comprises an nFET with horizontal p-doped nanosheet channels arranged in a first vertical stack, each horizontal p-doped nanosheet channel having a width W1, and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L1. The CFET structure further comprises a pFET with horizontal n-doped nanosheet channels arranged in a second vertical stack disposed on the first vertical stack, each horizontal n-doped nanosheet channel having a width W2, and connecting a second source contact to a second drain contact through a second GAA region having a length L2, wherein W2/L2 is not equal to W1/L1.

公开(公告)号：US20240105728A1

公开(公告)日：2024-03-28

申请号：US18472074

申请日：2023-09-21

Applicant: QUALCOMM Incorporated

Inventor： Qingqing LIANG ,  Haining YANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  George Pete IMTHURN ,  Jun YUAN ,  Giridhar NALLAPATI ,  Deepak SHARMA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11853 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.

公开(公告)号：US20210305155A1

公开(公告)日：2021-09-30

申请号：US16834618

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Giridhar NALLAPATI ,  Peijie FENG

IPC: H01L23/522 ,  H01L21/768

Abstract: An integrated circuit (IC) is described. The IC includes a substrate having an active device having an active region. The IC also includes a middle-of-line (MOL) interconnect layer having a contact merge (CM) layer on a trench contact coupled to the active region of the active device. The IC further includes back-end-of-line (BEOL) interconnect layers on the MOL interconnect layer. The IC also includes a metal resistor in a via zero interconnect layer between a first BEOL interconnect and the MOL interconnect layer. The metal resistor is coupled to the active region through a first via zero on the CM layer, a second via zero on the metal resistor, and the first BEOL interconnect on the first via zero and the second via zero.

公开(公告)号：US20190305077A1

公开(公告)日：2019-10-03

申请号：US15937097

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： Peijie FENG ,  Junjing BAO ,  Ye LU ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

Abstract: A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.