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公开(公告)号：US09792215B2
公开(公告)日：2017-10-17
申请号：US14672133
申请日：2015-03-28
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward Podaima , Bohuslav Rychlik , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Meghal Varia , Serag Gadelrab
IPC: G06F12/12 , G06F12/0862 , G06F12/0875 , G06F12/10 , G06F12/1027
CPC classification number: G06F12/0862 , G06F12/0875 , G06F12/10 , G06F12/1027 , G06F2212/1021 , G06F2212/452 , G06F2212/602 , G06F2212/6028 , G06F2212/654 , G06F2212/684
Abstract: Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.
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公开(公告)号：US09747213B2
公开(公告)日：2017-08-29
申请号：US14725882
申请日：2015-05-29
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward Podaima , Bohuslav Rychlik , Carlos Javier Moreira , Serag Monier GadelRab , Paul Christopher John Wiercienski , Alexander Miretsky , Kyle John Ernewein
IPC: G06F12/12 , G06F12/0846 , G06F12/1036 , G06F12/109
Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.
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13.发明授权公开(公告)号：US11029745B2
公开(公告)日：2021-06-08
申请号：US16184934
申请日：2018-11-08
Applicant: QUALCOMM INCORPORATED
Inventor： Kyle Ernewein , Jason Edward Podaima , Francisco Perez , John Daniels , Alex Miler , Jeffrey Gemar , Rexford Alan Hill , Haoping Xu
IPC: G06F1/32 , G06F1/324 , G06F1/3228
Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.
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公开(公告)号：US10386904B2
公开(公告)日：2019-08-20
申请号：US15086054
申请日：2016-03-31
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward Podaima , Christophe Denis Bernard Avoinne , Manokanthan Somasundaram , Sina Dena , Paul Christopher John Wiercienski , Bohuslav Rychlik , Steven John Halter , Jaya Prakash Subramaniam Ganasan , Myil Ramkumar , Dipti Ranjan Pal
IPC: G06F1/26 , G06F1/10 , G06F1/324 , G06F1/3234 , G06F1/3287 , G06F12/08
Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
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Patent Agency Ranking
公开(公告)号：US10037280B2
公开(公告)日：2018-07-31
申请号：US14726454
申请日：2015-05-29
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward Podaima , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Meghal Varia , Serag Gadelrab , Muhammad Umar Choudry
IPC: G06F12/08 , G06F12/10 , G06F12/0862 , G06F12/109
CPC classification number: G06F12/0862 , G06F12/10 , G06F12/109 , G06F2212/1021 , G06F2212/283 , G06F2212/312 , G06F2212/507 , G06F2212/6026 , G06F2212/608 , G06F2212/65 , G06F2212/654
Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.
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16.发明授权公开(公告)号：US10019380B2
公开(公告)日：2018-07-10
申请号：US14866228
申请日：2015-09-25
Applicant: QUALCOMM Incorporated
Inventor： Serag Monier GadelRab , Jason Edward Podaima , Ruolong Liu , Alexander Miretsky , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Simon Peter William Booth , Meghal Varia , Thomas David Dryburgh
IPC: G06F12/00 , G06F12/1072 , G06F13/00 , G06F13/28
CPC classification number: G06F12/1072 , G06F2212/1008 , G06F2212/1016
Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.
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公开(公告)号：US09910799B2
公开(公告)日：2018-03-06
申请号：US15089814
申请日：2016-04-04
Applicant: QUALCOMM Incorporated
Inventor： Christophe Avoinne , Jason Edward Podaima , Manokanthan Somasundaram , Bohuslav Rychlik , Thomas Zeng , Jaya Subramaniam Ganasan , Kun Xu
CPC classification number: G06F13/28 , G06F9/5016 , G06F9/5077 , G06F9/546 , G06F12/08 , G06F15/17318 , G06F2009/45583 , G06F2212/657
Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.
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公开(公告)号：US20170286335A1
公开(公告)日：2017-10-05
申请号：US15089814
申请日：2016-04-04
Applicant: QUALCOMM Incorporated
Inventor： Christophe Avoinne , Jason Edward Podaima , Manokanthan Somasundaram , Bohuslav Rychlik , Thomas Zeng , Jaya Subramaniam Ganasan , Kun Xu
CPC classification number: G06F13/28 , G06F9/5016 , G06F9/5077 , G06F9/546 , G06F12/08 , G06F15/17318 , G06F2009/45583 , G06F2212/657
Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.
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19.发明申请公开(公告)号：US20170091116A1
公开(公告)日：2017-03-30
申请号：US14866228
申请日：2015-09-25
Applicant: QUALCOMM Incorporated
Inventor： Serag Monier GadelRab , Jason Edward Podaima , Ruolong Liu , Alexander Miretsky , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Simon Peter William Booth , Meghal Varia , Thomas David Dryburgh
IPC: G06F12/10
CPC classification number: G06F12/1072 , G06F2212/1008 , G06F2212/1016
Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.
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