公开(公告)号：US20160035891A1

公开(公告)日：2016-02-04

申请号：US14448548

申请日：2014-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

Abstract: A fin field-effect transistor (FinFET) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material. The stressor material is confined by the capping material to a region proximate the gate stack. The stressor material provides stress on the semiconductor fin proximate the gate stack.

Abstract translation: 鳍状场效应晶体管（FinFET）包括在半导体鳍片的表面上的栅极堆叠。 半导体鳍片可以包括封盖材料和应力源材料。 应力源材料被封盖材料限制在靠近栅极叠层的区域。 应力源材料在靠近栅极堆叠的半导体鳍片上提供应力。

公开(公告)号：US20200044440A1

公开(公告)日：2020-02-06

申请号：US16362417

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Xiangdong CHEN ,  Haining YANG ,  Kern RIM

IPC: H02H9/04 ,  H01Q1/22 ,  H02J7/00

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

公开(公告)号：US20180082846A1

公开(公告)日：2018-03-22

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20160071795A1

公开(公告)日：2016-03-10

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20160005822A1

公开(公告)日：2016-01-07

申请号：US14321568

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Kern RIM ,  Zhongze WANG

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to a three-terminal semiconductor device including a self-aligned via for connecting to a gate terminal Hardmasks and spacers formed over top portions and sidewall portions of a drain connection to a drain terminal and a source connection to a source terminal protect and insulate the drain connection and the source connection, such that short circuits are avoided between the source and drain connections and the self-aligned via. The self-aligned via provides a direct metal-gate connection path between the gate terminal and a metal line such as a M1 metal line while avoiding a separate gate connection layer.

Abstract translation: 系统和方法涉及三端子半导体器件，其包括用于连接到栅极端子的自对准通孔。硬掩模和形成在到漏极端子的漏极连接的顶部和侧壁部分上的间隔物以及到源极端子的源极连接 保护和绝缘漏极连接和源极连接，从而避免在源极和漏极连接和自对准通孔之间产生短路。 自对准通孔在栅极端子和诸如M1金属线的金属线之间提供直接的金属栅极连接路径，同时避免了单独的栅极连接层。

公开(公告)号：US20150235948A1

公开(公告)日：2015-08-20

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Ohsang KWON ,  Kern RIM ,  John Jianhong ZHU ,  Xiangdong CHEN ,  Foua VANG ,  Raymond George STEPHANY ,  Choh Fei YEAP

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20150194525A1

公开(公告)日：2015-07-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US20200161189A1

公开(公告)日：2020-05-21

申请号：US16752157

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Stanley SONG ,  Jeffrey XU ,  Da YANG ,  Kern RIM ,  Choh fei YEAP

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

公开(公告)号：US20190295942A1

公开(公告)日：2019-09-26

申请号：US15933581

申请日：2018-03-23

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Kern RIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/532

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。