公开(公告)号：US20200294580A1

公开(公告)日：2020-09-17

申请号：US16299413

申请日：2019-03-12

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/419 ,  G11C16/08 ,  G11C16/12 ,  G11C16/04

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

公开(公告)号：US09865337B1

公开(公告)日：2018-01-09

申请号：US15466749

申请日：2017-03-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mukund Narasimhan ,  Raghav Gupta ,  Pradeep Raj ,  Rahul Sahu ,  Po-Hung Chen ,  Chulmin Jung

IPC: G11C5/10 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/417

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

公开(公告)号：US12047073B2

公开(公告)日：2024-07-23

申请号：US17922176

申请日：2021-04-29

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K5/00

CPC classification number: H03K3/012 ,  H03K5/01 ,  H03K17/56 ,  H03K2005/00078

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

公开(公告)号：US12020766B2

公开(公告)日：2024-06-25

申请号：US17654295

申请日：2022-03-10

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Hemant Patel ,  Diwakar Singh

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

公开(公告)号：US12020746B2

公开(公告)日：2024-06-25

申请号：US17675993

申请日：2022-02-18

Applicant: QUALCOMM Incorporated

Inventor： Rejeesh Ammanath Vijayan ,  Rahul Sahu ,  Pradeep Raj

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

公开(公告)号：US11955169B2

公开(公告)日：2024-04-09

申请号：US17210230

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

公开(公告)号：US11152921B1

公开(公告)日：2021-10-19

申请号：US17204421

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Veerabhadra Rao Boda ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: H03K3/00 ,  H03K3/037 ,  H03K5/14 ,  H03K19/20 ,  H03K3/286 ,  H03K3/356

Abstract: Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

公开(公告)号：US11049552B1

公开(公告)日：2021-06-29

申请号：US16827959

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4097 ,  G11C7/10 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

公开(公告)号：US10811086B1

公开(公告)日：2020-10-20

申请号：US16523350

申请日：2019-07-26

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Sharad Kumar Gupta ,  Rahul Sahu ,  Pradeep Raj ,  Veerabhadra Rao Boda ,  Adithya Bhaskaran ,  Akshdeepika

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

公开(公告)号：US09928898B2

公开(公告)日：2018-03-27

申请号：US15085942

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C16/08 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418 ,  G11C8/08 ,  G11C11/413 ,  G11C16/30

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  G11C16/08 ,  G11C16/30

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.