公开(公告)号：US20050073022A1

公开(公告)日：2005-04-07

申请号：US10642916

申请日：2003-08-18

Applicant: Olov Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

Inventor： Olov Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC classification number: H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

Abstract translation: 形成在半导体材料层中的浅沟槽隔离区。 浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。 还公开了形成浅沟槽隔离区域的方法。

公开(公告)号：US06872613B1

公开(公告)日：2005-03-29

申请号：US10654689

申请日：2003-09-04

Applicant: Qi Xiang ,  Huicai Zhong ,  Jung-Suk Goo ,  Allison K. Holbrook ,  Joong S. Jeon ,  George J. Kluth

Inventor： Qi Xiang ,  Huicai Zhong ,  Jung-Suk Goo ,  Allison K. Holbrook ,  Joong S. Jeon ,  George J. Kluth

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

Abstract translation: 根据一个示例性实施例，一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。 该方法还包括在电介质层上沉积第一金属层。 该方法还包括在第一金属层上沉积第二金属层。 该方法还包括在衬底的NMOS区域中注入氮气，并将第一金属层的第一部分转变为金属氧化物层，并将第一金属层的第二部分转换为金属氮化物层。 该方法还包括形成NMOS栅极和PMOS栅极，其中NMOS栅极包括一段金属氮化物层，PMOS栅极包括金属氧化物层的一段。

公开(公告)号：US20050054164A1

公开(公告)日：2005-03-10

申请号：US10658611

申请日：2003-09-09

Applicant: Qi Xiang

Inventor： Qi Xiang

IPC: H01L21/265 ,  H01L21/268 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L21/26586 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/785

Abstract: Processing is performed during fabrication of a strained silicon NMOS device to create point defects in silicon germanium portions of source regions, and optionally of drain regions, prior to activation of source and drain region dopants. The point defects retard diffusion of the n-type dopants in the silicon germanium material, effectively lengthening the duration of the diffusivity transient region and resulting in lower overall dopant diffusivity during activation.

Abstract translation: 在制造应变硅NMOS器件期间进行处理，以在源极和漏极区掺杂剂激活之前在源极区的硅锗部分中以及任选的漏极区产生点缺陷。 点缺陷阻碍了硅锗材料中n型掺杂剂的扩散，有效地延长了扩散性瞬态区的持续时间，并且在激活期间导致较低的总掺杂剂扩散率。

公开(公告)号：US06811448B1

公开(公告)日：2004-11-02

申请号：US10619879

申请日：2003-07-15

Applicant: Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

Inventor： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

IPC: H01L21302

CPC classification number: H01L21/02054 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/28518 ,  H01L29/665

Abstract: A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.

Abstract translation: 制造系统利用用于从晶片顶表面去除自然氧化物的协议。 暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。 该方案可以使用氟化氢浸渍。 在使用等离子体之前可以使用氟化氢浸渍。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06800910B2

公开(公告)日：2004-10-05

申请号：US10335474

申请日：2002-12-31

Applicant: Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

Inventor： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

IPC: H01L27105

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract translation: FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。 然后在硅锗FinFET体上形成硅的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：US06797602B1

公开(公告)日：2004-09-28

申请号：US10071207

申请日：2002-02-11

Applicant: George Jonathan Kluth ,  Qi Xiang

Inventor： George Jonathan Kluth ,  Qi Xiang

IPC: H01L213205

CPC classification number: H01L29/6653 ,  H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.

Abstract translation: 在源极/漏极延伸和金属硅化物触点中具有过饱和浓度的掺杂剂的晶体管等半导体器件能够生产更小更高速度的器件。 在高温金属硅化物接触形成期间，过饱和源极/漏极延伸部分从源极/漏极延伸部分扩散出来。 低温金属硅化物接触（例如硅化镍接触）的形成防止掺杂剂扩散，并且在整个半导体器件制造过程中将源极/漏极延伸部保持在过饱和状态。

公开(公告)号：US06787423B1

公开(公告)日：2004-09-07

申请号：US10314331

申请日：2002-12-09

Applicant: Qi Xiang

Inventor： Qi Xiang

IPC: H01L21336

CPC classification number: H01L29/1054 ,  H01L21/76232 ,  H01L29/0653

Abstract: High-speed semiconductor devices with reduced source/drain junction capacitance and reduced junction leakage based on strain silicon technology are fabricated by extending a shallow trench isolation region under the strained silicon layer. Embodiments include anisotropically etching the trench region and subsequently isotropically etching the trench to form laterally extending regions under the strained silicon layer. Embodiments also include filling the trench with an insulating material such that an air pocket is formed in the trench.

Abstract translation: 通过在应变硅层下面扩展浅沟槽隔离区域，制造出具有较低源极/漏极结电容和基于应变硅技术的减少结漏电的半导体器件。 实施例包括各向异性蚀刻沟槽区域，随后各向同性蚀刻沟槽，以在应变硅层下方形成横向延伸的区域。 实施例还包括用绝缘材料填充沟槽，使得在沟槽中形成气穴。

公开(公告)号：US06764912B1

公开(公告)日：2004-07-20

申请号：US09919943

申请日：2001-08-02

Applicant: John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

Inventor： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656

Abstract: The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.

Abstract translation: 栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。 通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

公开(公告)号：US06743689B1

公开(公告)日：2004-06-01

申请号：US10341427

申请日：2003-01-14

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

Abstract: Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

Abstract translation: 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。

公开(公告)号：US06696348B1

公开(公告)日：2004-02-24

申请号：US10314326

申请日：2002-12-09

Applicant: Qi Xiang

Inventor： Qi Xiang

IPC: H01L2176

CPC classification number: H01L21/76232

Abstract: The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer.

Abstract translation: 本发明能够制造改进的高速半导体器件。 本发明提供了由应变硅技术提供的更高速度，以及由浅沟槽隔离技术提供的较小的整体器件尺寸，而不会通过将浅沟槽隔离横向延伸到浅沟槽隔离部分而使弛豫与浅沟槽隔离区域相邻的应变硅层的部分松弛 覆盖硅锗层的应变硅层。