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    MOVING-PICTURE DECODING PROCESSING APPARATUS, MOVING-PICTURE CODING PROCESSING APPARATUS, AND OPERATING METHOD OF THE SAME
    14.
    发明申请
    MOVING-PICTURE DECODING PROCESSING APPARATUS, MOVING-PICTURE CODING PROCESSING APPARATUS, AND OPERATING METHOD OF THE SAME 审中-公开
    移动图像解码处理装置，移动图像编码处理装置及其操作方法

    公开(公告)号：US20150117549A1

    公开(公告)日：2015-04-30

    申请号：US14518110

    申请日：2014-10-20

    Applicant: Renesas Electronics Corporation

    Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Toshiyuki KAYA ,  Tetsuya SHIBAYAMA

    IPC: H04N19/44

    CPC classification number: H04N19/436 ,  H04N19/44

    Abstract: The present invention is directed to reduce deterioration in parallel processing capability. In a moving-picture decoding processing apparatus, information of a first plurality of frames and a second plurality of frames is supplied from a decoding control unit to first and second decoding processing units. For decoding the information from an intermediate point to an end point of a second preceding frame by the second decoding unit in a third period, use of a result of the process of the first decoding processing unit in the third period is inhibited, and use of a result of the process of a first preceding frame by the first decoding processing unit in a second period is permitted by an end signal. By reach of the intermediate point of the decoding of the second preceding frame by the second decoding processing unit in the second period, information from the start point to the intermediate point of the first subsequent frame included in the plural frames is decoded by the first decoding unit in the third period.

    Abstract translation: 本发明旨在减少并行处理能力的恶化。 在运动图像解码处理装置中，将第一多个帧和第二多个帧的信息从解码控制单元提供给第一和第二解码处理单元。 为了在第三时段中由第二解码单元从第二前一帧的中间点到终点的信息解码，禁止在第三周期中使用第一解码处理单元的处理结果，并且使用 结束信号允许由第一解码处理单元在第二时段中的第一前一帧的处理结果。 在第二时段中，通过第二解码处理单元对第二前一帧的解码的中间点的到达，通过第一解码对来自包含在多个帧中的第一后续帧的起始点到中间点的信息进行解码 单位在第三期。

    SEMICONDUCTOR DEVICE AND HARDWARE VIRTUALIZATION METHOD
    15.
    发明公开
    SEMICONDUCTOR DEVICE AND HARDWARE VIRTUALIZATION METHOD 审中-公开

    公开(公告)号：US20230176883A1

    公开(公告)日：2023-06-08

    申请号：US17938475

    申请日：2022-10-06

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Ryuichi IGARASHI ,  Kenichi TAKEDA ,  Katsushige MATSUBARA ,  Tetsuya SHIBAYAMA

    IPC: G06F9/455 ,  G06F9/4401

    CPC classification number: G06F9/45541 ,  G06F9/4406

    Abstract: According to one embodiment, a semiconductor device restricts an OS capable of using a functional block by an OS identifier written in an attribute register for restricting an accessible OS, and creates operation setting values of a first input unit, a second input unit, and a screen synthesis unit per OS to describe them in a setting value list stored in a shared memory, and each of the first input unit, second input unit, and screen synthesis unit has a mask circuit that refers to the OS identifier of the attribute register and in which write of the operation setting values into the setting register group of an own block is hampered, the operation setting values being described in the setting value list created by an OS other than the OS having a use authority for the own block.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    16.
    发明申请
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权

    公开(公告)号：US20210294691A1

    公开(公告)日：2021-09-23

    申请号：US16821915

    申请日：2020-03-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsushige MATSUBARA ,  Ryoji HASHIMOTO ,  Takahiro IRITA ,  Kenichi SHIMADA ,  Tetsuya SHIBAYAMA

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F9/30

    Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

    SEMICONDUCTOR DEVICE, ALLOCATION METHOD, AND DISPLAY SYSTEM
    19.
    发明申请
    SEMICONDUCTOR DEVICE, ALLOCATION METHOD, AND DISPLAY SYSTEM 审中-公开

    公开(公告)号：US20180041357A1

    公开(公告)日：2018-02-08

    申请号：US15631284

    申请日：2017-06-23

    Applicant: Renesas Electronics Corporation

    Inventor： Tetsuji TSUDA ,  Masaru HASE ,  Yuki INOUE ,  Katsushige MATSUBARA

    IPC: H04L12/28 ,  G11C5/04 ,  G11C29/02 ,  G06F11/30

    CPC classification number: H04L12/2856 ,  G06F11/3034 ,  G11C5/04 ,  G11C29/025 ,  H01L2224/16 ,  H01L2924/1305

    Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.

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