公开(公告)号：US20190006496A1

公开(公告)日：2019-01-03

申请号：US15980635

申请日：2018-05-15

Applicant: Renesas Electronics Corporation

Inventor： Ryo KANDA ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/08

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.

公开(公告)号：US20180182719A1

公开(公告)日：2018-06-28

申请号：US15833289

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Ryo KANDA

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H02M7/5387

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/495 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54486 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48155 ,  H01L2224/48245 ,  H01L2224/4903 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H02M7/003 ,  H02M7/5387 ,  H02M2001/0009 ,  H02P27/06

Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

公开(公告)号：US20180138828A1

公开(公告)日：2018-05-17

申请号：US15867978

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Koji BANDO ,  Takamitsu KANAZAWA ,  Ryo KANDA ,  Akihiro TAMURA ,  Hirobumi MINEGISHI

IPC: H02M7/537 ,  H01L23/04 ,  H02M7/00 ,  H01L27/06

CPC classification number: H02M7/537 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/49541 ,  H01L27/0664 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H02M7/003 ,  H02M7/53875 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

公开(公告)号：US20180122727A1

公开(公告)日：2018-05-03

申请号：US15858493

申请日：2017-12-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukihiro SATO ,  Akira MUTO ,  Ryo KANDA ,  Takamitsu KANAZAWA

IPC: H01L23/495 ,  H01L29/739 ,  H01L23/31 ,  H01L25/075 ,  H01L27/06 ,  H02P27/06

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

公开(公告)号：US20170104474A1

公开(公告)日：2017-04-13

申请号：US15387270

申请日：2016-12-21

Applicant: Renesas Electronics Corporation

Inventor： Ryo KANDA ,  Tetsu TODA ,  Junichi NAKAMURA ,  Kazuyuki UMEZU ,  Tomonobu KURIHARA ,  Takahiro NAGATSU ,  Yasushi NAKAHARA ,  Yoshinori KAYA

IPC: H03K3/356 ,  H03K17/567 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06

CPC classification number: H03K3/356182 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7823 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H02P27/06 ,  H03K5/24 ,  H03K17/567 ,  H03K17/6872 ,  H03K19/018521

Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.

公开(公告)号：US20170033035A1

公开(公告)日：2017-02-02

申请号：US15174568

申请日：2016-06-06

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATO ,  Akira MUTO ,  Ryo KANDA ,  Takamitsu KANAZAWA

IPC: H01L23/495 ,  H01L29/739 ,  H01L27/06 ,  H01L23/31

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L25/0753 ,  H01L27/0664 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4903 ,  H01L2224/49111 ,  H02P27/06

Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

Abstract translation: 提高半导体器件的可靠性。 芯片安装部TAB5布置成向+ x方向侧移动。 此外，半导体芯片CHP1（LV）的栅电极焊盘和半导体芯片CHP3的焊盘通过导线W1a和导线W1b通过继电器引线RL1电耦合。 同样地，半导体芯片CHP1（LW）的栅电极焊盘和半导体芯片CHP3的焊盘通过引线W1c和引线W1d通过继电器引线RL2电耦合。 此时，从密封体MR露出的继电器引线RL1，RL2的部分的结构与作为密封体MR的多个引线LD1，LD2的密封体MR露出的各部分的结构不同 外部端子。

公开(公告)号：US20160056818A1

公开(公告)日：2016-02-25

申请号：US14832867

申请日：2015-08-21

Applicant: Renesas Electronics Corporation

Inventor： Ryo KANDA ,  Tetsu TODA ,  Junichi NAKAMURA ,  Kazuyuki UMEZU ,  Tomonobu KURIHARA ,  Takahiro NAGATSU ,  Yasushi NAKAHARA ,  Yoshinori KAYA

IPC: H03K17/687 ,  H02P27/06 ,  H03K17/567 ,  H03K19/0185 ,  H03K5/24

CPC classification number: H03K3/356182 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7823 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H02P27/06 ,  H03K5/24 ,  H03K17/567 ,  H03K17/6872 ,  H03K19/018521

Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.

Abstract translation: 为了降低包括诸如驱动器IC的半导体器件的电力控制装置以及电子系统的成本等，驱动器IC包括高侧驱动器，电平移位电路，第一和第二晶体管， 和比较器电路。 第一晶体管形成在终端区域中。 第二晶体管形成在终端区域中并由第一电源电压驱动。 当感测节点的电压低于第一电源电压时，比较器电路形成在第一区域中以驱动第一晶体管导通，同时当感测节点的电压更高时驱动第一晶体管截止 比第一个电源电压。 第二晶体管是凹陷型晶体管。

公开(公告)号：US20150008539A1

公开(公告)日：2015-01-08

申请号：US14325003

申请日：2014-07-07

Applicant: Renesas Electronics Corporation

Inventor： Ryo KANDA ,  Tetsu TODA ,  Yasushi NAKAHARA ,  Yoshinori KAYA

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.