公开(公告)号：US20170153838A1

公开(公告)日：2017-06-01

申请号：US15355322

申请日：2016-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Ryoji HASHIMOTO ,  Toshiyuki KAYA ,  Kimihiko NAKAZAWA ,  Takahiro IRITA ,  Tetsuji TSUDA

IPC: G06F3/06 ,  G06F7/544

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673 ,  G06F7/544 ,  G06F2207/544 ,  H04N19/423

Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.

公开(公告)号：US20160156926A1

公开(公告)日：2016-06-02

申请号：US14906901

申请日：2013-07-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryoji HASHIMOTO ,  Kenichi IWATA ,  Kazushi AKIE

IPC: H04N19/563 ,  H04N19/61 ,  H04N19/86 ,  H04N19/42 ,  H04N19/115 ,  H04N19/119 ,  H04N19/146 ,  H04N19/159 ,  H04N19/52 ,  H04N19/91

CPC classification number: H04N19/563 ,  H04N19/11 ,  H04N19/115 ,  H04N19/119 ,  H04N19/124 ,  H04N19/132 ,  H04N19/146 ,  H04N19/159 ,  H04N19/167 ,  H04N19/176 ,  H04N19/42 ,  H04N19/436 ,  H04N19/52 ,  H04N19/59 ,  H04N19/61 ,  H04N19/86 ,  H04N19/91

Abstract: A moving image encoding apparatus executes moving image encoding of a syntax element relating to a moving image signal VS to form an encoded bitstream CVBS. Padding processing of adding padding processing data PD to the moving image signal VS is executed prior to the moving image encoding, and the horizontal and vertical sizes of an additional moving image signal added the padding processing data are set to an integral multiple of an encoded block size in the moving image encoding. It is determined that the encoded block of the syntax element belongs to which of the moving image signal VS and the padding processing data PD. In a case where the encoded block belongs to the former, an encoded bitstream having a large code amount is formed. In a case where the encoded block belongs to the latter, an encoded bitstream having a small code amount is formed.

Abstract translation: 运动图像编码装置执行与运动图像信号VS相关的语法元素的运动图像编码，以形成编码比特流CVBS。 在运动图像编码之前执行将填充处理数据PD添加到运动图像信号VS的填充处理，并且将添加了填充处理数据的附加运动图像信号的水平和垂直尺寸设置为编码块的整数倍 尺寸在运动图像编码。 确定语法元素的编码块属于运动图像信号VS和填充处理数据PD中的哪一个。 在编码块属于前者的情况下，形成具有大码量的编码比特流。 在编码块属于后者的情况下，形成具有小代码量的编码比特流。

公开(公告)号：US20240331080A1

公开(公告)日：2024-10-03

申请号：US18589997

申请日：2024-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi UEDA ,  Ryoji HASHIMOTO ,  Kaito MORI

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: The video data processing device includes at least one first functional module that performs first processing preset for each first processing unit data, at least one second functional module that performs second processing preset for each second processing unit data smaller than the first processing unit data, and a control unit that controls the execution order of pipeline processing for the first processing unit data by controlling the timing at which the first function module and the second function module operate. The control unit controls the subsequent stage so that the first function module and the second module are started in response to the completion of the respective processing in accordance with the end of the pre-stage.

公开(公告)号：US20200233471A1

公开(公告)日：2020-07-23

申请号：US16842399

申请日：2020-04-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi UEDA ,  Ryoji HASHIMOTO ,  Taku MAEKAWA ,  Katsushige MATSUBARA ,  Keisuke MATSUMOTO

IPC: G06F1/24 ,  G06T1/60 ,  G06T1/20

Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.

公开(公告)号：US20180184080A1

公开(公告)日：2018-06-28

申请号：US15798160

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Toshiyuki KAYA ,  Seiji MOCHIZUKI ,  Katsushige MATSUBARA ,  Ryoji HASHIMOTO ,  Ren IMAOKA

IPC: H04N17/00 ,  H04N5/232 ,  H04N17/02

CPC classification number: H04N17/004 ,  G06F3/14 ,  G06T1/20 ,  G09G3/2037 ,  G09G2330/10 ,  G09G2330/12 ,  G09G2340/02 ,  H04N1/32283 ,  H04N5/23293 ,  H04N9/045 ,  H04N17/02 ,  H04N19/89 ,  H04N2209/042

Abstract: An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values. The image processor compares the hash values between multiple frames so as to decide whether the screens have changed or stopped. A failure is detected when the screens are stopped.

公开(公告)号：US20180150428A1

公开(公告)日：2018-05-31

申请号：US15884576

申请日：2018-01-31

Applicant: Renesas Electronics Corporation

Inventor： Takahiko SUGIMOTO ,  Tomohiro UNE ,  Hiroshi UEDA ,  Ryoji HASHIMOTO ,  Toshiyuki KAYA

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4221 ,  G06F13/00 ,  G06F13/4009 ,  G06F13/4027

Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.