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    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210143260A1

    公开(公告)日：2021-05-13

    申请号：US17084097

    申请日：2020-10-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L29/10 ,  H01L21/28

    Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开

    公开(公告)号：US20190279998A1

    公开(公告)日：2019-09-12

    申请号：US16278951

    申请日：2019-02-19

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hideaki YAMAKOSHI ,  Shinichiro ABE ,  Takashi HASHIMOTO ,  Yuto OMIZU

    IPC: H01L27/11573 ,  H01L27/12 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/792 ,  H01L27/02

    Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210151609A1

    公开(公告)日：2021-05-20

    申请号：US17084163

    申请日：2020-10-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/792 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/78

    Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    17.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200051905A1

    公开(公告)日：2020-02-13

    申请号：US16655606

    申请日：2019-10-17

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L23/522 ,  H01L27/11517 ,  H01L21/768 ,  H01L23/532 ,  H01L21/762 ,  H01L49/02 ,  H01L27/11573 ,  H01L29/94 ,  H01L27/12

    Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    18.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160118394A1

    公开(公告)日：2016-04-28

    申请号：US14989999

    申请日：2016-01-07

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

    IPC: H01L27/115 ,  H01L27/092 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    19.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140242796A1

    公开(公告)日：2014-08-28

    申请号：US14079120

    申请日：2013-11-13

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

    IPC: H01L21/3105 ,  H01L27/105 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的半导体器件和制造方法

    公开(公告)号：US20140209996A1

    公开(公告)日：2014-07-31

    申请号：US14242500

    申请日：2014-04-01

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kota FUNAYAMA ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

    Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

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