公开(公告)号：US20210302801A1

公开(公告)日：2021-09-30

申请号：US16829509

申请日：2020-03-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA ,  Yasutaka NAKASHIBA

IPC: G02F1/225 ,  G02F1/025

Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.

公开(公告)号：US20200043847A1

公开(公告)日：2020-02-06

申请号：US16505228

申请日：2019-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Teruhiro KUWAJIMA

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.

公开(公告)号：US20180138325A1

公开(公告)日：2018-05-17

申请号：US15797230

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Shinichi WATANUKI ,  Futoshi KOMATSU ,  Tomoo NAKAYAMA ,  Takashi OGURA ,  Teruhiro KUWAJIMA

IPC: H01L31/028 ,  H01L31/0232 ,  H01L31/02

CPC classification number: H01L31/028 ,  H01L31/02005 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/105

Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.

公开(公告)号：US20170148732A1

公开(公告)日：2017-05-25

申请号：US15333750

申请日：2016-10-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L23/5227 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/1203 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate and including a plurality of wiring layers, and a first coil, a second coil, and a third coil which are formed above the semiconductor substrate. In a region located under the first coil and overlapping the first coil in plan view, the second and third coils CL2a and CL2b are disposed. The second and third coils are foamed in the same layer and electrically coupled in series to each other. Each of the second and third coils and the first coil are not coupled to each other via a conductor, but are magnetically coupled to each other.

公开(公告)号：US20160056107A1

公开(公告)日：2016-02-25

申请号：US14832397

申请日：2015-08-21

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro KUWAJIMA

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5223 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first interlayer insulating film, a barrier insulating film formed over the first interlayer insulating film to cover the wiring and the electrode, a second interlayer insulating film formed over the barrier insulating film, and a second wiring and a second electrode for the capacitive element embedded in the second interlayer insulating film. The lower surface of the second wiring is positioned in the middle of the thickness of the second interlayer layer film, and the lower surface of the second electrode is in contact with the barrier insulating film. The barrier insulating film of a portion interposed between both electrodes functions as a capacitance insulating film of the capacitive element and is thicker than the barrier insulating film of a portion covering the first wiring.

Abstract translation: 其布线结构包括第一层间绝缘膜，第一布线和嵌入在第一层间绝缘膜中的电容元件的第一电极，形成在第一层间绝缘膜上以覆盖布线和电极的阻挡绝缘膜， 形成在所述阻挡绝缘膜上的第二层间绝缘膜，以及用于所述第二层间绝缘膜中的所述电容性元件的第二布线和第二电极。 第二布线的下表面位于第二层间膜的厚度的中间，第二电极的下表面与阻挡绝缘膜接触。 插入在两个电极之间的部分的阻挡绝缘膜用作电容性元件的电容绝缘膜，并且比覆盖第一布线的部分的阻挡绝缘膜厚。