公开(公告)号：US06989588B2

公开(公告)日：2006-01-24

申请号：US09963049

申请日：2001-09-24

申请人： Maria C. Y. Quinones ,  Consuelo N. Tangpuz

发明人： Maria C. Y. Quinones ,  Consuelo N. Tangpuz

IPC分类号： H01L23/02 ,  H01L23/495

CPC分类号： H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device including a leadframe and a die coupled thereto. A drain pad is coupled to the drain region of the die in a body that substantially envelopes the leadframe and the die. The body includes a window defined therein. The body is placed around the leadframe and the die such that a surface of the drain pad opposite the die is exposed through the window.

公开(公告)号：US07501702B2

公开(公告)日：2009-03-10

申请号：US10876248

申请日：2004-06-24

申请人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

发明人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC分类号： H01L29/495

CPC分类号： H01L23/562 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/97 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

摘要翻译： 集成晶体管模块包括限定至少一个低侧焊盘和至少一个高侧焊盘的引线框架。 引线框架的台阶部分将低边和高边平台机械地和电气地互连。 低侧晶体管安装在低侧焊盘上，其漏极电连接到低侧焊盘。 高侧晶体管安装在高侧焊盘上，其源极与高侧焊盘电连接。

公开(公告)号：US20110095417A1

公开(公告)日：2011-04-28

申请号：US12607294

申请日：2009-10-28

申请人： Jocel P. Gomez ,  Consuelo N. Tangpuz

发明人： Jocel P. Gomez ,  Consuelo N. Tangpuz

IPC分类号： H01L23/498

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/03 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.

摘要翻译： 本文件尤其涉及一种半导体管芯，该半导体管芯具有耦合到半导体管芯的第一管芯表面处的第一电端子的第一导电凸块和基本上覆盖第一管芯表面并且基本上围绕第一导电凸块的电介质。 电介质的表面可以包括凹入的端子区域，并且第二电端子可以耦合到凹入端子区域中的第一导电凸块。

公开(公告)号：US20090117690A1

公开(公告)日：2009-05-07

申请号：US12349140

申请日：2009-01-06

申请人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

发明人： Rajeev D. Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC分类号： H01L21/00 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/97 ,  H01L25/072 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

摘要翻译： 集成晶体管模块包括限定至少一个低侧焊盘和至少一个高侧焊盘的引线框架。 引线框架的台阶部分将低边和高边平台机械地和电气地互连。 低侧晶体管安装在低侧焊盘上，其漏极电连接到低侧焊盘。 高侧晶体管安装在高侧焊盘上，其源极与高侧焊盘电连接。

公开(公告)号：US06423623B1

公开(公告)日：2002-07-23

申请号：US09141184

申请日：1998-08-27

申请人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

发明人： Izak Bencuya ,  Maria Christina B. Estacio ,  Steven P. Sapp ,  Consuelo N. Tangpuz ,  Gilmore S. Baje ,  Rey D. Maligro

IPC分类号： H01L2144

CPC分类号： H01L24/06 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

摘要翻译： 一种显着降低封装电阻的封装技术。 根据本发明，封装外部的引线框架与封装模制件内的硅芯片表面上的焊球直接接触，消除了电阻线互连。 本发明的封装技术特别适用于功率晶体管。