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    MEMORY DEVICE HAVING STORAGE FOR AN ERROR CODE CORRECTION EVENT COUNT
    11.
    发明申请
    MEMORY DEVICE HAVING STORAGE FOR AN ERROR CODE CORRECTION EVENT COUNT 审中-公开
    具有错误代码校正事件计数的存储器的存储器件

    公开(公告)号：US20150331732A1

    公开(公告)日：2015-11-19

    申请号：US14707348

    申请日：2015-05-08

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  Kurt T. Knorpp

    IPC: G06F11/07 ,  G11C11/406

    CPC classification number: G11C11/40618 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0787 ,  G11C11/406 ,  G11C2211/4062

    Abstract: An integrated circuit memory device is disclosed. The memory device includes at least one group of storage cells. Logic derives a count of error code correction events for each of the at least one group of storage cells. Storage stores the count. A memory control interface selectively communicates the count to a memory controller.

    Abstract translation: 公开了一种集成电路存储器件。 存储器件包括至少一组存储单元。 逻辑导出对于至少一组存储单元中的每一个的错误代码校正事件的计数。 存储存储计数。 存储器控制接口选择性地将计数传送到存储器控制器。

    Method and apparatus for calibrating write timing in a memory system
    12.
    发明授权
    Method and apparatus for calibrating write timing in a memory system 有权
    用于校准存储器系统中的写入定时的方法和装置

    公开(公告)号：US09177632B2

    公开(公告)日：2015-11-03

    申请号：US14714722

    申请日：2015-05-18

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

    IPC: G06F12/00 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G06F12/06

    CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

    Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

    Memory modules and systems with variable-width data ranks and configurable data-rank timing
    13.
    发明授权
    Memory modules and systems with variable-width data ranks and configurable data-rank timing 有权

    公开(公告)号：US12210467B2

    公开(公告)日：2025-01-28

    申请号：US18480344

    申请日：2023-10-03

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

    Protocol including a command-specified timing reference signal
    16.
    发明授权
    Protocol including a command-specified timing reference signal 有权

    公开(公告)号：US11816047B2

    公开(公告)日：2023-11-14

    申请号：US17191469

    申请日：2021-03-03

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Thomas J. Giovannini

    IPC: G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22

    CPC classification number: G06F13/1689 ,  G06F12/00 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

    Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

    Signal receiver with skew-tolerant strobe gating
    19.
    发明授权
    Signal receiver with skew-tolerant strobe gating 有权

    公开(公告)号：US11127444B1

    公开(公告)日：2021-09-21

    申请号：US16995612

    申请日：2020-08-17

    Applicant: Rambus Inc.

    Inventor： Andrew Fuller ,  Robert E. Palmer ,  Thomas J. Giovannini ,  Michael D. Bucher ,  Thoai Thai Le

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

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