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11.
公开(公告)号:US20140103397A1
公开(公告)日:2014-04-17
申请号:US14141648
申请日:2013-12-27
申请人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
CPC分类号: H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译: 公开了用于形成非平面锗量子阱结构的技术。 特别地,量子阱结构可以用IV或III-V族半导体材料实现,并且包括锗鳍结构。 在一个示例性情况下,提供了非平面量子阱器件,其包括具有衬底(例如硅上的SiGe或GaAs缓冲器),IV或III-V材料阻挡层(例如,SiGe或GaAs或 AlGaAs),掺杂层(例如,掺杂Δ/调制)和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构,以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号:US08575596B2
公开(公告)日:2013-11-05
申请号:US13647952
申请日:2012-10-09
申请人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号: H01L31/00
CPC分类号: H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译: 公开了用于形成非平面锗量子阱结构的技术。 特别地,量子阱结构可以用IV或III-V族半导体材料实现,并且包括锗鳍结构。 在一个示例性情况下,提供了非平面量子阱器件,其包括具有衬底(例如硅上的SiGe或GaAs缓冲器),IV或III-V材料阻挡层(例如,SiGe或GaAs或 AlGaAs),掺杂层(例如,掺杂Δ/调制)和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构,以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号:US08283653B2
公开(公告)日:2012-10-09
申请号:US12646477
申请日:2009-12-23
申请人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号: H01L29/06
CPC分类号: H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译: 公开了用于形成非平面锗量子阱结构的技术。 特别地,量子阱结构可以用IV或III-V族半导体材料实现,并且包括锗鳍结构。 在一个示例性情况下,提供了非平面量子阱器件,其包括具有衬底(例如硅上的SiGe或GaAs缓冲器),IV或III-V材料阻挡层(例如,SiGe或GaAs或 AlGaAs),掺杂层(例如,掺杂Δ/调制)和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构,以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号:US20110147711A1
公开(公告)日:2011-06-23
申请号:US12646477
申请日:2009-12-23
申请人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
发明人: Ravi Pillarisetty , Jack T. Kavalieros , Willy Rachmady , Uday Shah , Benjamin Chu-Kung , Marko Radosavljevic , Niloy Mukherjee , Gilbert Dewey , Been Y. Jin , Robert S. Chau
IPC分类号: H01L29/06 , H01L21/338
CPC分类号: H01L29/775 , B82Y10/00 , H01L21/76 , H01L29/0653 , H01L29/1054 , H01L29/155 , H01L29/165 , H01L29/267 , H01L29/517 , H01L29/66431 , H01L29/66439 , H01L29/66477 , H01L29/66795 , H01L29/66977 , H01L29/7782 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
摘要翻译: 公开了用于形成非平面锗量子阱结构的技术。 特别地,量子阱结构可以用IV或III-V族半导体材料实现,并且包括锗鳍结构。 在一个示例性情况下,提供了非平面量子阱器件,其包括具有衬底(例如硅上的SiGe或GaAs缓冲器),IV或III-V材料阻挡层(例如,SiGe或GaAs或 AlGaAs),掺杂层(例如,掺杂Δ/调制)和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构,以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。
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公开(公告)号:US09634007B2
公开(公告)日:2017-04-25
申请号:US14302350
申请日:2014-06-11
申请人: Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
发明人: Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L29/66 , H01L29/78 , H01L21/02 , H01L21/762 , H01L27/092 , H01L21/8258 , H01L29/423 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L29/775 , H01L29/06 , H01L21/8238
CPC分类号: H01L21/845 , B82Y10/00 , B82Y40/00 , H01L21/02639 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.
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公开(公告)号:US08765563B2
公开(公告)日:2014-07-01
申请号:US13630527
申请日:2012-09-28
申请人: Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
发明人: Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L21/00 , H01L21/311 , H01L21/8222 , H01L21/30 , H01L21/20 , H01L29/15
CPC分类号: H01L21/845 , B82Y10/00 , B82Y40/00 , H01L21/02639 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.
摘要翻译: 沟槽限制的选择性外延生长工艺,其中半导体器件层的外延生长在沟槽的范围内进行。 在实施例中,制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。 接种表面周围的半导体区域可以相对于接种表面凹陷,其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。 在形成沟槽的实施例中,牺牲性硬掩模翅片可以被覆盖在电介质中,然后将其平坦化以暴露硬掩模翅片,然后将其去除以暴露接种表面。 通过选择性异质外延从种子表面形成半导体器件层。 在实施例中,通过使隔离电介质的顶表面凹陷,从半导体器件层形成非平面器件。 在实施例中,可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。
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公开(公告)号:US09337291B2
公开(公告)日:2016-05-10
申请号:US14821561
申请日:2015-08-07
申请人: Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
发明人: Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
IPC分类号: H01L29/66 , H01L29/423 , H01L29/165 , H01L29/06 , H01L29/205 , H01L29/78 , H01L29/786
CPC分类号: H01L29/78609 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/165 , H01L29/205 , H01L29/42392 , H01L29/66742 , H01L29/785 , H01L29/78606 , H01L29/78618 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
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公开(公告)号:US09356099B2
公开(公告)日:2016-05-31
申请号:US14334636
申请日:2014-07-17
申请人: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号: H01L29/15 , H01L29/41 , H01L29/78 , H01L29/66 , H01L29/778 , H01L29/775 , H01L29/417 , H01L29/423 , H01L29/51
CPC分类号: H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
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公开(公告)号:US08809836B2
公开(公告)日:2014-08-19
申请号:US13758974
申请日:2013-02-04
申请人: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号: H01L29/66
CPC分类号: H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极,源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程,由本文所描述的技术提供的所得到的源极和漏极触点是自对准的,因为每个触点与栅电极对准并且被隔离 通过间隔材料。
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公开(公告)号:US20140326953A1
公开(公告)日:2014-11-06
申请号:US14334636
申请日:2014-07-17
申请人: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人: Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号: H01L29/15 , H01L29/417 , H01L29/78
CPC分类号: H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极,源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程,由本文所描述的技术提供的所得到的源极和漏极触点是自对准的,因为每个触点与栅电极对准并且被隔离 通过间隔材料。
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