公开(公告)号：US3988613A

公开(公告)日：1976-10-26

申请号：US573842

申请日：1975-05-02

申请人： Dale M. Brown ,  Mario Ghezzo ,  Marvin Garfinkel

发明人： Dale M. Brown ,  Mario Ghezzo ,  Marvin Garfinkel

IPC分类号： H01L27/108 ,  H01L27/148 ,  H01L27/14

CPC分类号： H01L27/108 ,  H01L27/14862

摘要： An array of radiation sensing devices, each including a pair of conductor-insulator-semiconductor capacitors, arranged in rows and columns in which the row stripes or lines form row connected capacitors in relation to selected surface regions of a semiconductor substrate and in which the column stripes or lines form column connected capacitors in relation to the selected surface regions. Each of the row stripes overlies first portions of the selected surface regions of a respective row. Each of the column stripes overlies entirely the selected surface regions of a respective column.

摘要翻译： 辐射检测装置阵列，每个包括一对导体 - 绝缘体 - 半导体电容器，其布置成行和列，其中行条或线相对于半导体衬底的选定的表面区域形成行连接的电容器，并且其中列 条纹或线条相对于选定的表面区域形成列连接的电容器。 行条中的每一行都覆盖相应行的所选表面区域的第一部分。 每个列条都完全覆盖相应列的选定表面区域。

公开(公告)号：US5776275A

公开(公告)日：1998-07-07

申请号：US734558

申请日：1996-10-21

申请人： Vikram Bidare Krishnamurthy ,  Kyung Wook Paik ,  Mario Ghezzo ,  William Paul Kornrumpf ,  Eric Joseph Wildi

发明人： Vikram Bidare Krishnamurthy ,  Kyung Wook Paik ,  Mario Ghezzo ,  William Paul Kornrumpf ,  Eric Joseph Wildi

IPC分类号： H01P1/387 ,  H01P11/00 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  B29C65/48 ,  H01P1/383

CPC分类号： H01P1/387 ,  H01P11/00 ,  H05K1/0237 ,  H05K1/16 ,  H05K1/182 ,  Y10T29/4913 ,  Y10T29/49165

摘要： A magnetic circulator is incorporated into a multi-chip module using a microwave high density interconnect (HDI) structure. A prepackaged circulator can be inserted into a ready-made high density interconnected multi-chip module; this prepackaged circulator may use a stripline design having a signal line with two ground planes above and below the signal line, or a microstrip transmission line design having one signal line and one ground plane below the signal line. Alternatively a circulator can be manufactured directly in a high density interconnected multi-chip module, with a stripline, or a microstrip transmission line design.

摘要翻译： 使用微波高密度互连（HDI）结构将磁性循环器结合到多芯片模块中。 预先包装的循环器可以插入现成的高密度互连多芯片模块中; 该预包装循环器可以使用具有在信号线上方和下方具有两个接地层的信号线的带状线设计，或者具有在信号线下方具有一个信号线和一个接地层的微带传输线设计。 或者，循环器可以直接制造在具有带状线或微带传输线设计的高密度互连多芯片模块中。

公开(公告)号：US4583281A

公开(公告)日：1986-04-22

申请号：US711333

申请日：1985-03-13

申请人： Mario Ghezzo ,  Manjin J. Kim

发明人： Mario Ghezzo ,  Manjin J. Kim

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/95

CPC分类号： H01L21/76205 ,  H01L21/32 ,  Y10S148/086 ,  Y10S148/114 ,  Y10S148/117

摘要： A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region. By optimizing the thicknesses of the first and second layers of the three layered structure, lattice stresses in the active region resulting from thermal cycling of the device having layers with different thermal coefficients of expansion are reduced during field oxidation.

摘要翻译： 描述了在硅衬底中形成由二氧化硅场界定的有源区的方法。 在硅衬底中形成的台面的顶部提供三层结构，其包括与台面的顶部接触的第一二氧化硅薄层，覆盖在二氧化硅薄层上的第二较厚的氮化硅层，以及第三层 覆盖氮化硅层的二氧化硅层。 在三层结构和硅衬底的暴露表面上形成另一层氮化硅。 通过各向异性蚀刻第四层氮化硅，在台面和三层结构的侧面上形成氮化硅的间隔部分。 通过控制第一层，第二层和第三层的厚度，间隔部分的宽度被优化以防止有源区的横向氧化。 通过优化三层结构的第一层和第二层的厚度，在场氧化期间，具有不同热膨胀系数的层的器件的热循环产生的有源区中的晶格应力减小。

公开(公告)号：US4378565A

公开(公告)日：1983-03-29

申请号：US192881

申请日：1980-10-01

申请人： Mario Ghezzo ,  Ronald T. Jerdonek

发明人： Mario Ghezzo ,  Ronald T. Jerdonek

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L23/5222 ,  H01L21/32 ,  H01L21/76221 ,  H01L2924/0002

摘要： An integrated circuit structure for reducing propagation delay is described. Integrated circuits include at least a pair of regions in each of which are located a respective plurality of functional cells and which are spaced apart by an interconnection region in which interconnection lines are provided connecting elements of the functional cells of one functional cell region with elements of the functional cells of the other functional cell region. Field oxide is provided in the interconnection region substantially greater in thickness than the field oxide in the regions of the functional cells thereby substantially reducing the capacitance and hence propagation delay of the interconnection lines. Formation of the field oxide of the interconnection region independent of the formation of the field oxide in the functional cell regions enables optimization of the field oxide in the interconnection region for minimum propagation delay without compromising functional cell formation in the functional cell regions.

摘要翻译： 描述用于减少传播延迟的集成电路结构。 集成电路包括至少一对区域，其中每个区域分别位于相应的多个功能单元中，并且由互连区间隔开，在互连区域中，互连线被设置成连接一个功能单元区域的功能单元的元件， 其他功能细胞区域的功能细胞。 在互连区域中提供的场氧化物的厚度比功能单元的区域中的场氧化物大得多，从而大大降低了互连线的电容和因此的传播延迟。 互连区域的场氧化物的形成与功能单元区域中的场氧化物的形成无关，能够在不损害功能单元区域中的功能性细胞形成的情况下优化互连区域中的场氧化物的最小传播延迟。

公开(公告)号：US4333964A

公开(公告)日：1982-06-08

申请号：US187430

申请日：1980-09-15

申请人： Mario Ghezzo

发明人： Mario Ghezzo

IPC分类号： H01L29/78 ,  H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  B05D5/12 ,  H01L21/306

CPC分类号： H01L21/32 ,  H01L21/76205 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/114 ,  Y10S148/117 ,  Y10S438/954

摘要： A method of reducing lateral field oxidation in the vicinity of the active regions of integrated circuits is described. The method utilizes a three layered masking structure for masking the active regions during field oxidation including a first very thin layer of silicon nitride in contact with the active region of the substrate, a second thin layer of silicon dioxide overlying the very thin layer of silicon nitride, and a third thick layer of silicon nitride overlying the second layer of silicon dioxide.

摘要翻译： 描述了一种在集成电路的有源区附近减小横向场氧化的方法。 该方法利用三层掩模结构，用于在场氧化期间掩蔽有源区，包括与衬底的有源区接触的第一非常薄的氮化硅层，覆盖在非常薄的氮化硅层上的第二薄层二氧化硅 以及覆盖在第二层二氧化硅上的第三厚氮化硅层。

公开(公告)号：US4040893A

公开(公告)日：1977-08-09

申请号：US676367

申请日：1976-04-12

申请人： Mario Ghezzo

发明人： Mario Ghezzo

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L31/18 ,  H01L21/312 ,  B44C1/22

CPC分类号： H01L31/1884 ,  H01L21/31111 ,  H01L21/32134 ,  Y02E10/50

摘要： A method of etching a layer of material on the surface of a substrate of silicon dioxide utilizes an etch mask constituted of a binary silicate glass. The binary silicate glass is removed subsequent to the etching of the layer without affecting the substrate of silicon dioxide.

摘要翻译： 蚀刻二氧化硅衬底表面上的材料层的方法利用由二元硅酸盐玻璃构成的蚀刻掩模。 在层的蚀刻之后去除二元硅酸盐玻璃而不影响二氧化硅的衬底。

公开(公告)号：US3979240A

公开(公告)日：1976-09-07

申请号：US573843

申请日：1975-05-02

申请人： Mario Ghezzo

发明人： Mario Ghezzo

IPC分类号： H01L21/28 ,  H01L31/18 ,  C23F1/02

CPC分类号： H01L31/1884 ,  H01L21/28 ,  Y02E10/50

摘要： A method of etching a desired pattern in a layer of indium tin oxide formed on a substrate of a semiconductor or an insulating material in which the desired pattern is formed of a hardened photoresist on the layer of indium tin oxide and thereafter the substrate and the indium tin oxide layer with the hardened resist thereon is immersed in a solution of concentrated hydrobromic acid for a time sufficient to etch away the indium tin oxide unmasked by the hardened photoresist.

摘要翻译： 在半导体或绝缘材料的衬底上形成的铟锡氧化物层中的期望图案的蚀刻方法，其中所需图案由铟锡氧化物层上的硬化光致抗蚀剂形成，此后衬底和铟 将其上具有硬化的抗蚀剂的氧化锡层浸入浓氢溴酸的溶液中足以蚀刻除去由硬化的光致抗蚀剂掩蔽的氧化铟锡的时间。

公开(公告)号：US06067931A

公开(公告)日：2000-05-30

申请号：US743587

申请日：1996-11-04

申请人： Mario Ghezzo ,  Timothy Dietrich Page ,  Thomas Bert Gorczyca ,  Rolf Sverre Bergman ,  Himanshu Bachubhai Vakil ,  Charles Samuel Huey ,  Seth David Silverstein

发明人： Mario Ghezzo ,  Timothy Dietrich Page ,  Thomas Bert Gorczyca ,  Rolf Sverre Bergman ,  Himanshu Bachubhai Vakil ,  Charles Samuel Huey ,  Seth David Silverstein

IPC分类号： H01L21/22 ,  H01L21/00 ,  H01L21/26 ,  H01L21/324 ,  C23C16/00 ,  F27D1/00

CPC分类号： H01L21/67115

摘要： A thermal processor for at least one semiconductor wafer includes a reactor chamber having a material substantially transparent to light including a wavelength within the range of about 200 nanometers to about 800 nanometers for holding the at least one semiconductor wafer. A coating including a material substantially reflective of infrared radiation can be present on at least a portion of the reactor chamber. A light source provides radiant energy to the at least one semiconductor wafer through the coating and the reactor chamber. The light source can include an ultraviolet discharge lamp, a halogen infrared incandescent lamp, or a metal halide visible discharge lamp. The coating can be situated on an inner or outer surface of the reactor chamber. If the reactor chamber has inner and outer walls, the coating can be situated on either the inner wall or the outer wall.

摘要翻译： 用于至少一个半导体晶片的热处理器包括具有对包含在约200纳米至约800纳米范围内的波长的光基本上透明的材料的反应室，用于保持至少一个半导体晶片。 包含基本上反射红外辐射的材料的涂层可以存在于反应器室的至少一部分上。 光源通过涂层和反应室向至少一个半导体晶片提供辐射能。 光源可以包括紫外线放电灯，卤素红外线白炽灯或金属卤化物可见放电灯。 涂层可以位于反应器室的内表面或外表面上。 如果反应器室具有内壁和外壁，则涂层可以位于内壁或外壁上。

公开(公告)号：US5653841A

公开(公告)日：1997-08-05

申请号：US421180

申请日：1995-04-13

申请人： Vikram Bidare Krishnamurthy ,  Kyung Wook Paik ,  Mario Ghezzo ,  William Paul Kornrumpf ,  Eric Joseph Wildi

发明人： Vikram Bidare Krishnamurthy ,  Kyung Wook Paik ,  Mario Ghezzo ,  William Paul Kornrumpf ,  Eric Joseph Wildi

IPC分类号： H01P1/387 ,  H01P11/00 ,  H05K1/02 ,  H05K1/16 ,  H05K1/18 ,  B29C65/48 ,  B05D5/12 ,  B32B31/12 ,  H01P1/383

CPC分类号： H01P1/387 ,  H01P11/00 ,  H05K1/0237 ,  H05K1/16 ,  H05K1/182 ,  Y10T29/4913 ,  Y10T29/49165

摘要： A magnetic circulator is incorporated into a multi-chip module using a microwave high density interconnect (HDI) structure. A prepackaged circulator can be inserted into a ready-made high density interconnected multi-chip module; this prepackaged circulator may use a stripline design having a signal line with two ground planes above and below the signal line, or a microstrip transmission line design having one signal line and one ground plane below the signal line. Alternatively a circulator can be manufactured directly in a high density interconnected multi-chip module, with a stripline, or a microstrip transmission line design.

摘要翻译： 使用微波高密度互连（HDI）结构将磁性循环器结合到多芯片模块中。 预先包装的循环器可以插入现成的高密度互连多芯片模块中; 该预包装循环器可以使用具有在信号线上方和下方具有两个接地层的信号线的带状线设计，或者具有在信号线下方具有一个信号线和一个接地层的微带传输线设计。 或者，循环器可以直接制造在具有带状线或微带传输线设计的高密度互连多芯片模块中。

公开(公告)号：US4707455A

公开(公告)日：1987-11-17

申请号：US935372

申请日：1986-11-26

申请人： Joseph C. Tsang ,  Mario Ghezzo ,  Robert T. Fuller

发明人： Joseph C. Tsang ,  Mario Ghezzo ,  Robert T. Fuller

IPC分类号： H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/425

CPC分类号： H01L21/823892 ,  H01L21/033 ,  H01L27/0928

摘要： A method of fabricating a semiconductor device having a symmetric and complementary P-well and N-well. The novel method involves the introduction of a first dopant type into a semiconductor substrate directly through those regions of an oxide layer and a nitride layer which do not underlie a first mask layer. The first mask layer is removed and a second mask layer is formed. A complementary dopant type is then introduced into the semiconductor substrate directly through those regions of the oxide layer and nitride layer which do not underlie the second mask layer. The second mask layer is removed and the dopant ions are simultaneously subjected to thermal drive in to thereby form adjacent wells of opposite dopant type in the semiconductor substrate.

摘要翻译： 一种制造具有对称且互补的P阱和N阱的半导体器件的方法。 新颖的方法包括将直接通过不属于第一掩模层的氧化物层和氮化物层的那些区域直接引入半导体衬底。 去除第一掩模层并形成第二掩模层。 然后，将辅助掺杂剂类型直接通过不在第二掩模层下面的氧化物层和氮化物层的那些区域引入半导体衬底。 去除第二掩模层，同时对掺杂剂离子进行热驱动，从而在半导体衬底中形成相反掺杂剂类型的相邻阱。