公开(公告)号：US20220239224A1

公开(公告)日：2022-07-28

申请号：US17567130

申请日：2022-01-02

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/08 ,  H03K17/06

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

公开(公告)号：US20220239223A1

公开(公告)日：2022-07-28

申请号：US17560761

申请日：2021-12-23

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M3/158 ,  H02M1/38

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

公开(公告)号：US20220224325A1

公开(公告)日：2022-07-14

申请号：US17568637

申请日：2022-01-04

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H03K17/16

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

公开(公告)号：US20220223733A1

公开(公告)日：2022-07-14

申请号：US17547707

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Chun-Lung Chang ,  Chih-Wen Hsiung ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

公开(公告)号：US20210074851A1

公开(公告)日：2021-03-11

申请号：US16868456

申请日：2020-05-06

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Wei Chiu ,  Ta-Yung Yang ,  Wu-Te Weng ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chih-Wen Hsiung ,  Kuo-Chin Chiu ,  Chun-Lung Chang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

公开(公告)号：US09786776B2

公开(公告)日：2017-10-10

申请号：US15260599

申请日：2016-09-09

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC: H01L29/24 ,  H01L21/331 ,  H01L21/329 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L23/48 ,  H01L29/732 ,  H01L29/739 ,  H01L29/872

CPC classification number: H01L29/7787 ,  H01L23/481 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0843 ,  H01L29/1004 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/66212 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/66333 ,  H01L29/66462 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

公开(公告)号：US20240297067A1

公开(公告)日：2024-09-05

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US12062570B2

公开(公告)日：2024-08-13

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/7621 ,  H01L21/76221 ,  H01L21/76281 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7816

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US11955890B2

公开(公告)日：2024-04-09

申请号：US17567130

申请日：2022-01-02

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Ting-Wei Liao ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H02M1/38 ,  H02M1/00 ,  H02M1/08 ,  H02M3/158 ,  H03K17/06

CPC classification number: H02M3/158 ,  H02M1/0006 ,  H02M1/08 ,  H02M1/38 ,  H03K17/063 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

公开(公告)号：US20220223464A1

公开(公告)日：2022-07-14

申请号：US17547829

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.