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42 条记录 (耗时 0.032 秒)

    Structure for folded architecture pillar memory cell
    11.
    发明授权
    Structure for folded architecture pillar memory cell 有权
    折叠式立柱式记忆体结构

    公开(公告)号：US06440801B1

    公开(公告)日：2002-08-27

    申请号：US09604901

    申请日：2000-06-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

    IPC分类号： H01L21336

    CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

    摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

    摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

    Dual level error detection and correction employing data subsets from previously corrected data
    13.
    发明授权
    Dual level error detection and correction employing data subsets from previously corrected data 失效
    采用来自先前校正的数据的数据子集进行双电平误差检测和校正

    公开(公告)号：US5581567A

    公开(公告)日：1996-12-03

    申请号：US401297

    申请日：1995-03-09

    申请人： Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Willem B. van der Hoeven

    发明人： Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Willem B. van der Hoeven

    IPC分类号： G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G06F11/1008

    摘要： A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.

    摘要翻译： 一种提供额外数据位而不占用存储容量的存储器系统。 从存储器中取出第一个数据字，并进行纠正以消除任何单位错误。 然后取出第二数据字（其是被校正的第一数据字的子集），并且为第二数据字生成新的数据校正位（奇偶校验位或ECC校验位）。 输出第二数据字和新产生的数据校正位。 该结构通过更大的数据输出和相对于数据输出的较小的存储容量来摊销系统内数据校正的费用。

    Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
    14.
    发明授权
    Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
    容错计算机存储器系统和采用双级错误校正和检测功能的组件

    公开(公告)号：US5533036A

    公开(公告)日：1996-07-02

    申请号：US486628

    申请日：1995-06-07

    申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

    发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

    IPC分类号： G06F11/00 ,  G06F11/10

    CPC分类号： G06F11/1052 ,  G06F11/1008

    摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    摘要翻译： 在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个存储器单元都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正能力的装置来增强存储器可靠性 例如，响应于在一个存储器单元中出现不可校正的错误。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

    Three dimensional multichip package methods of fabrication
    16.
    发明授权
    Three dimensional multichip package methods of fabrication 失效
    三维多芯片封装方法的制作

    公开(公告)号：US5270261A

    公开(公告)日：1993-12-14

    申请号：US965728

    申请日：1992-10-23

    申请人： Claude L. Bertin ,  Paul A. Farrar, Sr. ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Willem B. van der Hoeven ,  Francis R. White

    发明人： Claude L. Bertin ,  Paul A. Farrar, Sr. ,  Howard L. Kalter ,  Gordon A. Kelley, Jr. ,  Willem B. van der Hoeven ,  Francis R. White

    IPC分类号： H01L25/065 ,  H01L21/60

    CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  Y10S148/135

    摘要： A fabrication method and resultant three-dimensional multichip package having a densely stacked array of semiconductor chips interconnected at least partially by means of a plurality of metallized trenches are disclosed. The fabrication method includes providing an integrated circuit chip having high aspect ratio metallized trenches therein extending from a first surface to a second surface thereof. An etch stop layer is provided proximate the termination position of the metallized trenches with the semiconductor substrate. Next the integrated circuit device is affixed to a carrier such that the surface of the supporting substrate is exposed and substrate is thinned from the integrated circuit device until exposing at least some of the plurality of metallized trenches therein. Electrical contact can thus be made to the active layer of the integrated circuit chip via the exposed metallized trenches. Specific details of the fabrication method and the resultant multichip package are set forth.

    摘要翻译： 公开了一种具有通过多个金属化沟槽至少部分互连的半导体芯片的密集堆叠阵列的制造方法和所得的三维多芯片封装。 制造方法包括提供其中从其第一表面延伸到其第二表面的具有高纵横比金属化沟槽的集成电路芯片。 在具有半导体衬底的金属化沟槽的终止位置附近提供蚀刻停止层。 接下来，集成电路器件被固定到载体上，使得支撑衬底的表面被暴露，并且衬底从集成电路器件变薄，直到暴露其中的多个金属化沟槽中的至少一些。 因此，可以通过暴露的金属化沟槽对集成电路芯片的有源层进行电接触。 阐述制造方法和所得多芯片封装的具体细节。

    Shadow ram cell having a shallow trench eeprom
    17.
    发明授权
    Shadow ram cell having a shallow trench eeprom 失效
    阴影柱塞细胞具有浅沟eeprom

    公开(公告)号：US5196722A

    公开(公告)日：1993-03-23

    申请号：US848913

    申请日：1992-03-12

    申请人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    发明人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/788

    CPC分类号： H01L27/10829 ,  H01L27/105 ,  H01L29/7881

    摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

    摘要翻译： 公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。 浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。 本发明的阵列提供高密度影子RAM。 还公开了用于制造本发明的装置的方法。

    Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty
    18.
    发明授权
    Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty 失效
    字线驱动禁止电路实现世界线冗余，而无需访问时间损失

    公开(公告)号：US5031151A

    公开(公告)日：1991-07-09

    申请号：US600944

    申请日：1990-10-22

    申请人： John A. Fifield ,  Howard L. Kalter ,  Christopher P. Miller ,  Steven W. Thomashot

    发明人： John A. Fifield ,  Howard L. Kalter ,  Christopher P. Miller ,  Steven W. Thomashot

    IPC分类号： G11C29/00

    CPC分类号： G11C29/84

    摘要： A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.

    摘要翻译： 描述了在不影响访问时间的情况下实现字线冗余的半导体存储器件。 冗余解码器电路产生禁止产生正常字线信号的字线驱动禁止信号。 取消选择也取消选择通常访问的参考单元，要求冗余单元提供自己的参考信号。 最后一个要求是通过利用双电池来实现冗余存储器。 将冗余存储器单元放置在位线隔离器的感测节点侧使得能够有效地加倍可用于正常存储器的多个子阵列中的每一个的冗余单元。

    Structures for wafer level test and burn-in
    19.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06426904B2

    公开(公告)日：2002-07-30

    申请号：US09803500

    申请日：2001-03-09

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。