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    Shadow ram cell having a shallow trench eeprom
    2.
    发明授权
    Shadow ram cell having a shallow trench eeprom 失效
    阴影柱塞细胞具有浅沟eeprom

    公开(公告)号：US5196722A

    公开(公告)日：1993-03-23

    申请号：US848913

    申请日：1992-03-12

    申请人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    发明人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/788

    CPC分类号： H01L27/10829 ,  H01L27/105 ,  H01L29/7881

    摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

    摘要翻译： 公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。 浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。 本发明的阵列提供高密度影子RAM。 还公开了用于制造本发明的装置的方法。

    Integrated memory cube, structure and fabrication
    3.
    发明授权
    Integrated memory cube, structure and fabrication 失效
    集成存储立方体，结构和制造

    公开(公告)号：US5563086A

    公开(公告)日：1996-10-08

    申请号：US406284

    申请日：1995-03-17

    申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

    发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

    IPC分类号： G11C5/00 ,  H01L25/065 ,  H01L21/70

    CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

    摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

    摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

    Stacked double dense read only memory
    4.
    发明授权
    Stacked double dense read only memory 失效
    堆叠双密度只读存储器

    公开(公告)号：US4603341A

    公开(公告)日：1986-07-29

    申请号：US530452

    申请日：1983-09-08

    申请人： Claude L. Bertin ,  Howard L. Kalter

    发明人： Claude L. Bertin ,  Howard L. Kalter

    IPC分类号： G11C17/08 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L29/78 ,  G11C17/00

    CPC分类号： H01L27/11519 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/112

    摘要： A read only memory array of stacked IGFET devices composed of first and second sub-arrays of field effect transistors. The first sub-array of first field effect transistors is formed in a substrate. Each of the first field effect transistor devices is responsive to a polysilicon gate electrode. The second sub-array of second field effect transistors is formed in a layer of laser annealed polysilicon material which overlies the first sub-array. The gate electrodes of the first field effect transistors act as the gate electrodes of the second field effect transistors.

    摘要翻译： 由场效应晶体管的第一和第二子阵列组成的堆叠IGFET器件的只读存储器阵列。 第一场效应晶体管的第一子阵列形成在衬底中。 第一场效应晶体管器件中的每一个都响应于多晶硅栅电极。 第二场效应晶体管的第二子阵列形成在覆盖在第一子阵列上的激光退火多晶硅材料层中。 第一场效应晶体管的栅电极用作第二场效应晶体管的栅电极。

    Integrated memory cube structure
    6.
    发明授权
    Integrated memory cube structure 失效
    集成内存立方体结构

    公开(公告)号：US5561622A

    公开(公告)日：1996-10-01

    申请号：US120993

    申请日：1993-09-13

    申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

    发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

    IPC分类号： G11C5/00 ,  H01L25/065 ,  G11C5/06 ,  H01L23/02

    CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

    摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

    摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

    Structures for wafer level test and burn-in
    7.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06426904B2

    公开(公告)日：2002-07-30

    申请号：US09803500

    申请日：2001-03-09

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    Complementary depletion switch body stack off-chip driver
    9.
    发明授权
    Complementary depletion switch body stack off-chip driver 失效
    互补耗尽开关体堆栈片外驱动

    公开(公告)号：US06177818B1

    公开(公告)日：2001-01-23

    申请号：US09303508

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H03B2100

    CPC分类号： H03K19/09482 ,  H03K19/00361 ,  H03K19/018521

    摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.

    摘要翻译： 包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。 大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。 第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。 固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。 从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。 在另一个实施例中，添加了反射/过冲传感器60。 传感器的输出连接到耗尽PFET和NFET的主体。 来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。 更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。