公开(公告)号：US08904666B1

公开(公告)日：2014-12-09

申请号：US12984212

申请日：2011-01-04

Applicant: Keith Rozell ,  Robert Warren ,  Chris Giusto

Inventor： Keith Rozell ,  Robert Warren ,  Chris Giusto

IPC: F26B19/00 ,  E04C2/38 ,  E04C2/54

CPC classification number: F26B25/12

Abstract: A dryer for drying various types of products such as food products and pet food. The dryer includes a frame structure, a conveyor disposed in the dryer, and a heating unit for supplying heat to the dryer. A plurality of relatively lightweight hygienic panels, including doors, is secured to the frame structure and form a part of the exterior of the dryer. The hygienic panels provide access to the interior of the dryer for cleaning and maintenance. Each hygienic panel is sealed so that moisture and air cannot enter the interior of the panel. Disposed inside each hygienic panel is a honeycomb panel and an insulating structure. The hygienic panel provides rigidity and strength to the hygienic panel and at the same time enables the panel to be of a relatively light weight construction.

Abstract translation: 用于干燥各种类型的产品如食品和宠物食品的烘干机。 干燥机包括框架结构，设置在干燥器中的输送机和用于向干燥器供热的加热单元。 多个相对较轻的卫生面板（包括门）固定到框架结构并形成干衣机外部的一部分。 卫生面板提供进入干衣机内部的清洁和维护。 每个卫生面板被密封，使得湿气和空气不能进入面板的内部。 每个卫生面板内设有蜂窝板和绝缘结构。 卫生面板为卫生面板提供刚性和强度，同时使面板具有相对较轻的结构。

公开(公告)号：US08412989B2

公开(公告)日：2013-04-02

申请号：US13438658

申请日：2012-04-03

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/02 ,  G11C29/00

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US20120266037A1

公开(公告)日：2012-10-18

申请号：US13438658

申请日：2012-04-03

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US08046647B2

公开(公告)日：2011-10-25

申请号：US12657642

申请日：2010-01-25

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/26

CPC classification number: G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract translation: 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和要测试的电路之间的测试控制电路; 其中测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：US08022490B2

公开(公告)日：2011-09-20

申请号：US12054169

申请日：2008-03-24

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H01L29/84

CPC classification number: G01L1/146 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  G01D5/24 ,  G01L9/0072 ,  G01P15/08 ,  G01P15/0975

Abstract: A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected to the conducting via, such that the plurality of ribbon conductors form a transducer array in combination with the conducting plane, such as through capacitive coupling that changes in response to changes in the physical shape of the plurality of ribbons.

Abstract translation: 提供了微机电传感器。 微电子机械传感器包括基板和设置在基板上的导电平面。 导电通孔设置在基板上，例如与导电平面相邻。 多个带状导体设置在导电平面上并电连接到导电通孔，使得多个带状导体与导电平面组合形成换能器阵列，例如通过电容耦合，其响应于 多个色带的物理形状。

公开(公告)号：US20070250802A1

公开(公告)日：2007-10-25

申请号：US11635369

申请日：2006-12-07

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H03K19/173

CPC classification number: H04L25/4902 ,  H03K5/135 ,  H04Q2213/13034 ,  H04Q2213/13076 ,  H04Q2213/13213 ,  H04Q2213/13214 ,  H04Q2213/13322 ,  H04Q2213/1336

Abstract: A method for routing signals comprising: supplying to an input of a routing block having multiple outputs an information signal comprising a first edge and a second edge on a single line, the first and second edges being separated by a time period which represents information conveyed by the signal, and one of the first and second edges providing timing information; controlling the routing block to select one of said multiple outputs; and transferring the signal to said selected one of said multiple outputs.

Abstract translation: 一种用于路由信号的方法，包括：向具有多个输出的路由块的输入提供包括在单个线路上的第一边缘和第二边缘的信息信号，所述第一和第二边缘被分隔一段时间段，所述时间段表示由 所述信号，并且所述第一和第二边缘之一提供定时信息; 控制所述路由块以选择所述多个输出中的一个; 以及将所述信号传送到所述多个输出中的所述选择的一个。

公开(公告)号：US20070198796A1

公开(公告)日：2007-08-23

申请号：US11359348

申请日：2006-02-22

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G11B5/09 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022

Abstract: Method and apparatus for transferring data. The apparatus preferably includes a first volatile memory block, a second volatile memory block coupled to a non-volatile circular buffer, and a controller configured to direct first data to the first volatile memory block for subsequent transfer to a downstream block, such as a data storage array. The controller is further configured to direct second data to the second volatile memory block for subsequent transfer to the non-volatile circular buffer. Preferably, the second volatile memory block forms a portion of a non-volatile random access memory (NVRAM) and the circular buffer is formed from a flash memory device. An intelligence block preferably controls said subsequent transfer of the second data from the second volatile memory block to the circular buffer. The second data are preferably transferred from the circular buffer to the downstream block in conjunction with the transfer of the first data.

Abstract translation: 用于传输数据的方法和装置。 该装置优选地包括第一易失性存储器块，耦合到非易失性循环缓冲器的第二易失性存储器块和被配置为将第一数据引导到第一易失性存储器块的控制器，用于随后传送到诸如数据的下游块 存储阵列。 控制器还被配置为将第二数据引导到第二易失性存储器块，以便随后传送到非易失性循环缓冲器。 优选地，第二易失性存储器块形成非易失性随机存取存储器（NVRAM）的一部分，并且循环缓冲器由闪存器件形成。 智能块优选地控制第二数据从第二易失性存储器块到循环缓冲器的所述后续传送。 结合第一数据的传送，第二数据优选地从循环缓冲器传送到下游块。

公开(公告)号：US20060220173A1

公开(公告)日：2006-10-05

申请号：US11097646

申请日：2005-04-01

Applicant: Qing Gan ,  Robert Warren ,  Anthony Lobianco ,  Steve Liang

Inventor： Qing Gan ,  Robert Warren ,  Anthony Lobianco ,  Steve Liang

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49822 ,  B81C1/00269 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16235 ,  H01L2224/2746 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32235 ,  H01L2224/73103 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

公开(公告)号：US20060036888A1

公开(公告)日：2006-02-16

申请号：US11175108

申请日：2005-07-05

Applicant: Robert Warren ,  David Smith

Inventor： Robert Warren ,  David Smith

IPC: G06F1/04

CPC classification number: G06F1/24

Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Abstract translation: 一种电子设备，其具有在第一时钟环境中工作的第一电路和在第二时钟环境中工作的第二电路，所述第一电路被布置为产生用于复位所述第二电路的软复位信号，所述集成电路还包括：软复位保持电路 连接在第一时钟环境中的时钟，以接收软复位信号并产生处于断言状态的输出复位信号; 以及在第二时钟环境中被时钟的同步器，连接以接收输出复位信号，并且在预定时间段之后产生处于断言状态的重新定时复位信号，其中重新定时复位信号被反馈到软复位保持电路以使输出 复位信号在所述预定周期结束时采取无效状态。

公开(公告)号：US20050283695A1

公开(公告)日：2005-12-22

申请号：US11101377

申请日：2005-04-07

Applicant: Robert Warren ,  Robert Mills

Inventor： Robert Warren ,  Robert Mills

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/04

CPC classification number: G01R31/318552

Abstract: An integrated circuit including test circuitry, the test circuitry including a counter for counting clock signals and having an output for providing a control signal. The counter being arranged to have an internal state, and the counter being arranged to change the control signal on the internal state of counter reaching a predetermined value.

Abstract translation: 包括测试电路的集成电路，测试电路包括用于计数时钟信号并具有用于提供控制信号的输出的计数器。 计数器被布置成具有内部状态，并且计数器被布置成在计数器的内部状态上改变控制信号达到预定值。