公开(公告)号：US11948994B2

公开(公告)日：2024-04-02

申请号：US17531903

申请日：2021-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US11626499B2

公开(公告)日：2023-04-11

申请号：US17524259

申请日：2021-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun Chung ,  Heonbok Lee ,  Chunghwan Shin ,  Youngsuk Chai ,  Sangjin Hyun

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.

公开(公告)号：US10985275B2

公开(公告)日：2021-04-20

申请号：US16503790

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weonhong Kim ,  Wandon Kim ,  Hyeonjun Baek ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US10950709B2

公开(公告)日：2021-03-16

申请号：US16458412

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk Yim ,  Wandon Kim ,  Weonhong Kim ,  Jongho Park ,  Hyeonjun Baek ,  Byounghoon Lee ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.

公开(公告)号：US10784260B2

公开(公告)日：2020-09-22

申请号：US16116295

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Wandon Kim ,  Jeonghyuk Yim ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.

公开(公告)号：US20190081148A1

公开(公告)日：2019-03-14

申请号：US15938716

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

公开(公告)号：US10043803B2

公开(公告)日：2018-08-07

申请号：US15372876

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L29/06 ,  H01L29/43 ,  H01L29/49 ,  H01L27/092 ,  H01L29/423

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：US20240250144A1

公开(公告)日：2024-07-25

申请号：US18585978

申请日：2024-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US12027524B2

公开(公告)日：2024-07-02

申请号：US18200986

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung Cho ,  Subin Shin ,  Donghyun Roh ,  Byung-Suk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US11901356B2

公开(公告)日：2024-02-13

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungha Oh ,  Pil-Kyu Kang ,  Kughwan Kim ,  Weonhong Kim ,  Yuichiro Sasaki ,  Sang Woo Lee ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L27/06 ,  H01L23/48 ,  H10B41/60 ,  H10B43/20 ,  H10B63/00

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H10B41/60 ,  H10B43/20 ,  H10B63/30 ,  H10B63/84

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).