Abstract:
A dielectric material includes a layered metal oxide including a first layer having a positive charge and a second layer having a negative charge, wherein the first layer and the second layer are alternately disposed; a monolayered nanosheet; a nanosheet laminate of the monolayered nanosheets; or a combination thereof, wherein the dielectric material includes a two-dimensional layered material having a two-dimensional crystal structure, wherein the two-dimensional layered material is represented by Chemical Formula 1 X2[A(n−1)MnO(3n+1)] Chemical Formula 1 wherein, in Chemical Formula 1, X is H, an alkali metal, a cationic polymer, or a combination thereof, A is Ca, Sr, La, Ta, or a combination thereof, M is La, Ta, Ti, or a combination thereof, and n≥1.
Abstract:
An electrically conductive thin film including a compound represented by Chemical Formula 1 and having a layered crystal structure: AxMyChz Chemical Formula 1 wherein A is V, Nb, or Ta, M is Ni, Co, Fe, Pd, Pt, Ir, Rh, Si, or Ge, Ch is S, Se, or Te, x is a number from 1 to 3, y is a number from 1 to 3, and z is a number from 2 to 14.
Abstract:
Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.
Abstract:
An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.
Abstract:
An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.
Abstract:
Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.
Abstract:
An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.
Abstract:
An electrical conductor includes: a first conductive layer including a plurality of ruthenium oxide nanosheets, wherein at least one ruthenium oxide nanosheet of the plurality of ruthenium oxide nanosheets includes a halogen, a chalcogen, a Group 15 element, or a combination thereof on a surface of the ruthenium oxide nanosheet.
Abstract:
An electrically conductive thin film including: a material including a compound represented by Chemical Formula 1 and having a layered crystal structure, MemAa Chemical Formula 1 wherein Me is Al, Ga, In, Si, Ge, Sn, A is S, Se, Te, or a combination thereof, and m and a each are independently a number selected so that the compound of Chemical Formula 1 is neutral; and a dopant disposed in the compound of Chemical Formula 1, wherein the dopant is a metal dopant that is different from Me and has an oxidation state which is greater than an oxidation state of Me, a non-metal dopant having a greater number of valence electrons than a number of valence electrons of A in Chemical Formula 1, or a combination thereof, and wherein the compound of Chemical Formula 1 includes a chemical bond which includes a valence electron of an s orbital of Me.