公开(公告)号：US09971530B1

公开(公告)日：2018-05-15

申请号：US15347552

申请日：2016-11-09

Applicant: SanDisk Technologies LLC

Inventor： Nian Niles Yang ,  Grishma Shah ,  Philip Reusswig ,  Sahil Sharma ,  Nan Lu

IPC: G06F3/06 ,  G11C16/28 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G06F11/00 ,  G06F11/30

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/004 ,  G06F11/3034 ,  G06F11/3058 ,  G06F2201/81 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3459

Abstract: A storage system and method for temperature throttling for block reading are provided. In one embodiment, a storage system is provided comprising a memory comprising a plurality of word lines and a controller in communication with the memory. The controller is configured to determine whether a temperature of the memory is above a first threshold temperature; and in response to determining that the temperature of the memory is above the first threshold temperature: apply a voltage to the plurality of word lines; and after the voltage has been applied, read one of the plurality of word lines. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US20180129431A1

公开(公告)日：2018-05-10

申请号：US15347552

申请日：2016-11-09

Applicant: SanDisk Technologies LLC

Inventor： Nian Niles Yang ,  Grishma Shah ,  Philip Reusswig ,  Sahil Sharma ,  Nan Lu

IPC: G06F3/06 ,  G11C16/28 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G06F11/00 ,  G06F11/30

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/004 ,  G06F11/3034 ,  G06F11/3058 ,  G06F2201/81 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3459

Abstract: A storage system and method for temperature throttling for block reading are provided. In one embodiment, a storage system is provided comprising a memory comprising a plurality of word lines and a controller in communication with the memory. The controller is configured to determine whether a temperature of the memory is above a first threshold temperature; and in response to determining that the temperature of the memory is above the first threshold temperature: apply a voltage to the plurality of word lines; and after the voltage has been applied, read one of the plurality of word lines. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US09711231B1

公开(公告)日：2017-07-18

申请号：US15191898

申请日：2016-06-24

Applicant: SanDisk Technologies LLC

Inventor： Chris Yip ,  Philip Reusswig ,  Nian Niles Yang ,  Grishma Shah ,  Abuzer Azo Dogan ,  Biswajit Ray ,  Mohan Dunga ,  Joanna Lai ,  Changyuan Chen

IPC: G11C16/26 ,  G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

公开(公告)号：US09672940B1

公开(公告)日：2017-06-06

申请号：US15240370

申请日：2016-08-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Phil Reusswig ,  Nian Niles Yang ,  Grishma Shah

IPC: G11C16/10 ,  G11C29/44 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2029/0411 ,  G11C2211/5621

Abstract: In response to a request to read data, the non-volatile memory system identifies the physical block that is storing the requested data. Read parameters associated with the physical block are also identified. The read parameters include bit error rate information. The memory system chooses whether to use a read process with a faster sense time or a read process with a slower sense time based on the bit error rate information and temperature data. The requested data is read from the identified physical block using the chosen read process configured by at least a subset of the read parameters.

公开(公告)号：US10347315B2

公开(公告)日：2019-07-09

申请号：US15800023

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Philip David Reusswig ,  Grishma Shah ,  Nian Niles Yang

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/00 ,  G11C11/4091

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.

公开(公告)号：US10339000B2

公开(公告)日：2019-07-02

申请号：US15264279

申请日：2016-09-13

Applicant: SanDisk Technologies LLC

Inventor： Nian Niles Yang ,  Grishma Shah ,  Philip Reusswig

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/13 ,  H03M13/37 ,  G06F3/06 ,  G06F12/02

Abstract: A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US20190163367A1

公开(公告)日：2019-05-30

申请号：US16262125

申请日：2019-01-30

Applicant: SanDisk Technologies LLC

Inventor： Alexander Bazarsky ,  Grishma Shah ,  Idan Alrod ,  Eran Sharon

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

公开(公告)号：US20190130964A1

公开(公告)日：2019-05-02

申请号：US15800023

申请日：2017-10-31

Applicant: SanDisk Technologies LLC

Inventor： Philip David Reusswig ,  Grishma Shah ,  Nian Niles Yang

IPC: G11C11/406 ,  G11C11/4091 ,  G11C29/00

CPC classification number: G11C11/40618 ,  G06F12/00 ,  G11C11/40603 ,  G11C11/4091 ,  G11C16/34 ,  G11C29/783

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.

公开(公告)号：US20180074891A1

公开(公告)日：2018-03-15

申请号：US15264279

申请日：2016-09-13

Applicant: SanDisk Technologies LLC

Inventor： Nian Niles Yang ,  Grishma Shah ,  Philip Reusswig

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

CPC classification number: G06F11/1068 ,  G06F3/0626 ,  G06F3/0652 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1032 ,  G06F11/1056 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/70 ,  G06F2212/702 ,  G06F2212/7205 ,  G11C29/52 ,  H03M13/13 ,  H03M13/2906 ,  H03M13/2918 ,  H03M13/2942 ,  H03M13/373 ,  H03M13/3761

Abstract: A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US20170371755A1

公开(公告)日：2017-12-28

申请号：US15191150

申请日：2016-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nian Niles Yang ,  Jiahui Yuan ,  Grishma Shah ,  Xinde Hu ,  Lanlan Gu ,  Bin Wu

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/10

CPC classification number: G06F11/2094 ,  G06F2201/805 ,  G06F2201/82 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/025 ,  G11C2029/1202

Abstract: A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.