公开(公告)号：US09910749B2

公开(公告)日：2018-03-06

申请号：US15191150

申请日：2016-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nian Niles Yang ,  Jiahui Yuan ,  Grishma Shah ,  Xinde Hu ,  Lanlan Gu ,  Bin Wu

IPC: G11C16/04 ,  G06F11/20 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

CPC classification number: G06F11/2094 ,  G06F2201/805 ,  G06F2201/82 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/025 ,  G11C2029/1202

Abstract: A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.

公开(公告)号：US20180053562A1

公开(公告)日：2018-02-22

申请号：US15240188

申请日：2016-08-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Phil Reusswig ,  Joanna Lai ,  Deepak Raghu ,  Grishma Shah ,  Nian Niles Yang

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C16/22 ,  G11C16/26

CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409

Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.

公开(公告)号：US09811267B1

公开(公告)日：2017-11-07

申请号：US15294313

申请日：2016-10-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nian Niles Yang ,  Grishma Shah ,  Phil Reusswig ,  Dmitry Vaysman

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F1/206 ,  G06F3/0655 ,  G06F3/0688 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3459 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a controller, one or more memory packages, a system temperature sensor, and one or more memory temperature sensors. The system temperature sensor is located at or on the controller. Each of the one or more memory temperature sensors are positioned at one of the one or more memory packages. The controller monitors system temperature using the system temperature sensor. If the system temperature is above a first threshold, then temperature is sensed at the memory packages using the one or more memory temperature sensors. Individual memory packages have their performance throttled if their temperature exceeds a second threshold.

公开(公告)号：US10026488B2

公开(公告)日：2018-07-17

申请号：US15240188

申请日：2016-08-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Phil Reusswig ,  Joanna Lai ,  Deepak Raghu ,  Grishma Shah ,  Nian Niles Yang

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C16/22 ,  G11C16/26

Abstract: A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb.

公开(公告)号：US10002649B1

公开(公告)日：2018-06-19

申请号：US15440975

申请日：2017-02-23

Applicant: SanDisk Technologies LLC

Inventor： Ronen Golan ,  Roie Shpaizman ,  Alex Bazarsky ,  Eli Elmoalem ,  Grishma Shah ,  Idan Alrod

IPC: G11C7/10 ,  G11C16/32 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C7/22 ,  G11C16/10 ,  G11C16/32 ,  G11C16/3459

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for providing a preliminary ready indication for non-volatile memory. A non-volatile memory element initiates a write operation for one or more storage cells of the non-volatile memory element. The non-volatile memory element determines whether a progress threshold is satisfied for the write operation. The non-volatile memory element provides a preliminary ready indication, indicating that the progress threshold is satisfied.

公开(公告)号：US20170309340A1

公开(公告)日：2017-10-26

申请号：US15628417

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Grishma Shah ,  Yan Li ,  Jian Chen ,  Kenneth Louie ,  Nian Niles Yang

IPC: G11C16/26 ,  H01L27/11556 ,  G11C11/56 ,  G06F12/0802 ,  H01L27/11582 ,  G11C16/04

CPC classification number: G11C7/1009 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1063 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563 ,  G11C2216/20

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

公开(公告)号：US11789612B2

公开(公告)日：2023-10-17

申请号：US16903196

申请日：2020-06-16

Applicant: SanDisk Technologies LLC

Inventor： Karin Inbar ,  Sahil Sharma ,  Grishma Shah

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679

Abstract: For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die.

公开(公告)号：US10732847B2

公开(公告)日：2020-08-04

申请号：US16262125

申请日：2019-01-30

Applicant: SanDisk Technologies LLC

Inventor： Alexander Bazarsky ,  Grishma Shah ,  Idan Alrod ,  Eran Sharon

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/04

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

公开(公告)号：US20210389879A1

公开(公告)日：2021-12-16

申请号：US16903196

申请日：2020-06-16

Applicant: SanDisk Technologies LLC

Inventor： Karin Inbar ,  Sahil Sharma ,  Grishma Shah

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die.

公开(公告)号：US10043558B2

公开(公告)日：2018-08-07

申请号：US15628417

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Grishma Shah ,  Yan Li ,  Jian Chen ,  Kenneth Louie ,  Nian Niles Yang

IPC: G11C7/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C7/1009 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1063 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563 ,  G11C2216/20

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.