公开(公告)号：US20220173071A1

公开(公告)日：2022-06-02

申请号：US17106884

申请日：2020-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A first bonding unit is provided, which includes a first substrate, a first passivation dielectric layer, and first bonding pads. A second bonding unit is provided, which includes a second substrate, a second passivation dielectric layer, and second bonding pads including bonding pillar structures. Solder material portions are formed on physically exposed surfaces of the first bonding pads. The second bonding unit is attached to the first bonding unit by bonding the at least one of the bonding pillar structures to a respective solder material portion.

公开(公告)号：US20220149002A1

公开(公告)日：2022-05-12

申请号：US17094543

申请日：2020-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin HOU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/00 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/50 ,  H01L23/532

Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

公开(公告)号：US20210351059A1

公开(公告)日：2021-11-11

申请号：US16867845

申请日：2020-05-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shoichi MURAKAMI ,  Shigeru NAKATSUKA ,  Syo FUKATA ,  Yusuke OSAWA ,  Shigehiro FUJINO ,  Masaaki HIGASHITANI

IPC: H01L21/683 ,  H01J37/32 ,  H01L21/67 ,  H01L21/66 ,  C23C16/509

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

公开(公告)号：US20210272912A1

公开(公告)日：2021-09-02

申请号：US16806087

申请日：2020-03-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam. A first subset of the silicon nitride material portions that is not irradiated with the laser beam includes first silicon nitride material portions that apply tensile stress to respective surrounding material portions, and the second subset of the silicon nitride material portions that is irradiated with the laser beam includes second silicon nitride material portions that apply compressive stress to respective surrounding material portions.

公开(公告)号：US20210143115A1

公开(公告)日：2021-05-13

申请号：US16682848

申请日：2019-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.

公开(公告)号：US20210066317A1

公开(公告)日：2021-03-04

申请号：US16552089

申请日：2019-08-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L27/1158 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514

Abstract: A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

公开(公告)号：US20200051993A1

公开(公告)日：2020-02-13

申请号：US16142752

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US20200006364A1

公开(公告)日：2020-01-02

申请号：US16019961

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI ,  Jayavel PACHAMUTHU

IPC: H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US20230223248A1

公开(公告)日：2023-07-13

申请号：US17573452

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Yujin TERASAWA ,  Naoki TAKEGUCHI ,  Kensuke YAMAGUCHI ,  Masaaki HIGASHITANI

IPC: H01L21/02 ,  C23C16/458

CPC classification number: H01L21/02175 ,  H01L21/02271 ,  C23C16/4583

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US20230164996A1

公开(公告)日：2023-05-25

申请号：US17534528

申请日：2021-11-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L29/15 ,  H01L29/205 ,  H01L27/11556 ,  G11C16/10

CPC classification number: H01L27/11582 ,  H01L29/158 ,  H01L29/205 ,  H01L27/11556 ,  G11C16/10

Abstract: A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.