公开(公告)号：US11322483B1

公开(公告)日：2022-05-03

申请号：US17090045

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Ken Oowada ,  Mitsuteru Mushiga

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11582 ,  H01L23/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

公开(公告)号：US10833100B2

公开(公告)日：2020-11-10

申请号：US16816552

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenji Sugiura ,  Mitsuteru Mushiga ,  Yuji Fukano ,  Akio Nishida

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11568 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/105 ,  H01L27/108

Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.

公开(公告)号：US20200312859A1

公开(公告)日：2020-10-01

申请号：US16362988

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka Otsu ,  Mitsuteru Mushiga ,  Yasushi Doda

IPC: H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  G11C5/06 ,  H01L21/8234 ,  H01L21/768

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each alternating stack within the plurality of alternating stacks is laterally spaced apart from one another by a network of interconnected trenches that extend through each level of the insulating layers and the electrically conductive layers. Groups of memory stack structures extend through a respective one of the alternating stacks. The network of interconnected trenches includes first lengthwise trenches laterally extending along a first horizontal direction by a first lateral trench extension distance, second lengthwise trenches laterally extending along the first horizontal direction and interlaced with the first lengthwise trenches to provide a laterally alternating sequence, and widthwise trenches connecting an end of a respective one of the second lengthwise trenches to a portion of a sidewall of a first lengthwise trench. The staircase regions provide a compact layout.

公开(公告)号：US10553599B1

公开(公告)日：2020-02-04

申请号：US16142875

申请日：2018-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhen Chen ,  Michiaki Sano ,  Mitsuteru Mushiga

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11565 ,  H01L21/311

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.

公开(公告)号：US20190326313A1

公开(公告)日：2019-10-24

申请号：US16024048

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Kiyohiko Sakakibara ,  Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US20190280003A1

公开(公告)日：2019-09-12

申请号：US16020817

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kensuke Yamaguchi ,  James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.

公开(公告)号：US10354987B1

公开(公告)日：2019-07-16

申请号：US15928340

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11556

Abstract: Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.

公开(公告)号：US10354980B1

公开(公告)日：2019-07-16

申请号：US15928407

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L25/065 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/00 ,  H01L21/822

Abstract: Multiple semiconductor chips can be bonded through copper-to-copper bonding. The multiple semiconductor chips include a logic chip and multiple memory chips. The logic chip includes a peripheral circuitry for operation of memory devices within the multiple memory chips. The memory chips can include front side bonding pad structures, backside bonding pad structures, and sets of metal interconnect structures providing electrically conductive paths between pairs of a first side bonding pad structure and a backside bonding pad structure. Thus, electrical control signal can vertically propagate between the logic chip and an overlying memory chip through at least one intermediate memory chip located between them. The backside bonding pad structures can be formed as portions of integrated through-substrate via and pad structures that extend through a respective semiconductor substrate.

公开(公告)号：US11889684B2

公开(公告)日：2024-01-30

申请号：US16951325

申请日：2020-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Shinsuke Yada ,  Mitsuteru Mushiga ,  Akio Nishida ,  Hiroyuki Ogawa ,  Teruo Okina

IPC: H10B41/27 ,  H01L29/06 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

公开(公告)号：US11501821B2

公开(公告)日：2022-11-15

申请号：US17090080

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Ken Oowada ,  Mitsuteru Mushiga

IPC: G11C16/06 ,  G11C11/408 ,  G11C5/06 ,  G11C5/02 ,  G11C11/4094

Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.