公开(公告)号：US09959915B2

公开(公告)日：2018-05-01

申请号：US15151617

申请日：2016-05-11

Applicant: SanDisk Technologies LLC

Inventor： Amul Desai ,  Hao Nguyen ,  Man Mui ,  Ohwon Kwon

IPC: G11C7/00 ,  G11C7/12 ,  H01L27/02 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/12 ,  G05F1/463 ,  G11C7/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/22 ,  H01L27/0211

Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

公开(公告)号：US20240331741A1

公开(公告)日：2024-10-03

申请号：US18346359

申请日：2023-07-03

Applicant: SanDisk Technologies LLC

Inventor： Iris Lu ,  Yonggang Wu ,  Kou Tei ,  Ohwon Kwon

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1048 ,  G11C7/1039 ,  G11C7/12

Abstract: Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.

公开(公告)号：US11798638B2

公开(公告)日：2023-10-24

申请号：US17484218

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/10 ,  H10B43/27

Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.

公开(公告)号：US20230326531A1

公开(公告)日：2023-10-12

申请号：US17718124

申请日：2022-04-11

Applicant: SanDisk Technologies LLC

Inventor： Yanjie Wang ,  Ohwon Kwon ,  Kou Tei ,  Tai-Yuan Tseng ,  Yasue Yamamoto ,  Yonggang Wu ,  Guirong Liang

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3459 ,  H01L25/0657

Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

公开(公告)号：US20230101019A1

公开(公告)日：2023-03-30

申请号：US17484218

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56

Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.

公开(公告)号：US11521675B1

公开(公告)日：2022-12-06

申请号：US17349009

申请日：2021-06-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kou Tei ,  Anirudh Amarnath ,  Ohwon Kwon

IPC: G11C7/00 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

Abstract: A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.

公开(公告)号：US20210104271A1

公开(公告)日：2021-04-08

申请号：US16593576

申请日：2019-10-04

Applicant: SanDisk Technologies LLC

Inventor： Ohwon Kwon ,  Kou Tei ,  VSNK Chaitanya G.

IPC: G11C11/4074 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/56

Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.

公开(公告)号：US11881266B2

公开(公告)日：2024-01-23

申请号：US17667169

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.

公开(公告)号：US11837296B2

公开(公告)日：2023-12-05

申请号：US17505179

申请日：2021-10-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Ohwon Kwon

IPC: G11C16/04 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

公开(公告)号：US20230253053A1

公开(公告)日：2023-08-10

申请号：US17667169

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/24 ,  H01L27/11556

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.