公开(公告)号：US20230261015A1

公开(公告)日：2023-08-17

申请号：US18305959

申请日：2023-04-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Kyle THOMAS ,  David T. PRICE ,  Rusty WINZENREAD ,  Bruce GREENWOOD

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14636 ,  H01L27/14634

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

公开(公告)号：US20220367534A1

公开(公告)日：2022-11-17

申请号：US17302836

申请日：2021-05-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  Michael Gerard KEYES ,  Ryan RETTMANN ,  Kevin MCSTAY

IPC: H01L27/146

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

公开(公告)号：US20210111106A1

公开(公告)日：2021-04-15

申请号：US16675525

申请日：2019-11-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. Price ,  Jeffery A. NEULS ,  Dean E. PROBST ,  Santosh MENON ,  Peter A. BURKE ,  Bigildis DOSDOS

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/11 ,  H01L25/00

Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

公开(公告)号：US20250125284A1

公开(公告)日：2025-04-17

申请号：US18488628

申请日：2023-10-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  James Joseph STEFFES

IPC: H01L23/60 ,  H01L23/00 ,  H01L27/146

Abstract: A semiconductor device may include a first chip with a first wafer and a first dielectric layer, and a second chip that includes a second wafer and a second dielectric layer, the second chip having a backside surface and a frontside surface opposed to the backside surface and bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. The semiconductor device may include a die seal layer on the backside surface having a die seal ground contact in contact with the second wafer, and an electrostatic discharge path that includes the die seal layer, the die seal ground contact, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line.

公开(公告)号：US20240371905A1

公开(公告)日：2024-11-07

申请号：US18309933

申请日：2023-05-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Swarnal BORTHAKUR ,  Marc Allen SULFRIDGE ,  Jeffrey Peter GAMBINO ,  Vladimir KOROBOV ,  Richard MAURITZSON ,  David T. PRICE

IPC: H01L27/146 ,  H01L23/58

Abstract: A semiconductor device may include a first chip that includes a first wafer and a first dielectric layer disposed thereon. The semiconductor device may include a second chip that includes a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. An opening through the backside surface of the second chip may extend into the second dielectric layer, and a bond pad may be disposed within the second dielectric layer between the second wafer and the bond line.

公开(公告)号：US20240321924A1

公开(公告)日：2024-09-26

申请号：US18673521

申请日：2024-05-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  David T. PRICE ,  Marc Allen SULFRIDGE ,  Richard MAURITZSON ,  Michael Gerard KEYES ,  Ryan RETTMANN ,  Kevin MCSTAY

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/1464

Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

公开(公告)号：US20210215749A1

公开(公告)日：2021-07-15

申请号：US16739507

申请日：2020-01-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Gavin HALL ,  Thomas F. LONG ,  Renaud André Jean Albert GILLON ,  Santosh MENON

IPC: G01R31/00 ,  H01L27/02 ,  G01R31/27 ,  G01R31/26

Abstract: An event-recording circuit for recording electrical events experienced by an internal circuit in a semiconductor device is disclosed. The event-recording circuit is coupled to the internal circuit via a spark gap circuit. The spark gap circuit includes one or more encapsulated air-gap structures that are fabricated using a process flow that matches, or is adapted from, a process flow used in fabricating the semiconductor device. The event-recording circuit further includes a recording device that has an electrical property that is changed by a signal passed by the spark gap circuit, such as an ESD or EOS signal. Accordingly, a test may be performed to determine the presence, and in some cases the extent, of the change to the electrical property in a failure analysis of the semiconductor device.

公开(公告)号：US20190043903A1

公开(公告)日：2019-02-07

申请号：US16116634

申请日：2018-08-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Angel RODRIGUEZ ,  David T. PRICE ,  Jeffery Allen NEULS ,  Kenneth Andrew BATES ,  Rick MAURITZSON

IPC: H01L27/146 ,  H01L27/06

CPC classification number: H01L27/14609 ,  H01L27/0617 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636

Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

公开(公告)号：US20180219038A1

公开(公告)日：2018-08-02

申请号：US15421505

申请日：2017-02-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Kyle THOMAS ,  David T. PRICE ,  Rusty WINZENREAD ,  Bruce GREENWOOD

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14634 ,  H01L27/14636

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

公开(公告)号：US20240297099A1

公开(公告)日：2024-09-05

申请号：US18648132

申请日：2024-04-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jeffrey Peter GAMBINO ,  Swarnal BORTHAKUR

IPC: H01L23/48 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/4814 ,  H01L25/18

Abstract: A structure includes a semiconductor substrate having a through-substrate via (TSV) extending from a backside of the semiconductor substrate up to an insulator layer disposed on a frontside of the semiconductor substrate. The insulator layer is exposed at a bottom of the TSV and an insulating liner is disposed on a sidewall of the TSV. A spacer layer is disposed conformally on the insulating liner on the sidewall and the bottom of the TSV, and a contact opening is formed through the spacer layer and the insulator layer at the bottom of TSV. The contact opening extends from the bottom of TSV through the insulator layer to a metal pad inside the insulator layer. A layer of the conductive material is deposited in the contact opening and on the sidewall of the TSV forming a vertical interconnection from the backside of the semiconductor substrate to the metal pad.