公开(公告)号：US20230273637A1

公开(公告)日：2023-08-31

申请号：US18024198

申请日：2021-08-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Takuro KANEMURA ,  Hidefumi RIKIMARU ,  Takayuki IKEDA ,  Yuto YAKUBO ,  Shunpei YAMAZAKI

IPC: G05F3/24 ,  H01M10/42

CPC classification number: G05F3/24 ,  H01M10/425

Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes. The third capacitor retains a voltage applied to the back gate by being applied with a voltage for polarization inversion in the ferroelectric layer.

公开(公告)号：US20220352865A1

公开(公告)日：2022-11-03

申请号：US17765046

申请日：2020-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki OHSHIMA ,  Hitoshi KUNITAKE ,  Yuto YAKUBO ,  Takayuki IKEDA

IPC: H03H7/38 ,  H01L21/822 ,  H01L21/02 ,  H03F3/60 ,  H03F3/19 ,  H01L27/088

Abstract: An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.

公开(公告)号：US20220246185A1

公开(公告)日：2022-08-04

申请号：US17606116

申请日：2020-05-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Seiya SAITO ,  Tatsuya ONUKI

IPC: G11C7/12 ,  H01L27/108

Abstract: Provision of a novel semiconductor device. The semiconductor device includes a first control circuit including a first transistor using a silicon substrate for a channel; a second control circuit provided over the first control circuit, which includes a second transistor using a metal oxide for a channel; a memory circuit provided over the second control circuit, which includes a third transistor using a metal oxide for a channel; and a global bit line and an inverted global bit line that have a function of transmitting a signal between the first control circuit and the second control circuit. The first control circuit includes a sense amplifier circuit including an input terminal and an inverted input terminal. In a first period for reading data from the memory circuit to the first control circuit, the second control circuit controls whether the global bit line and the inverted global bit line from which electric charge is discharged are charged or not in accordance with the data read from the memory circuit.

公开(公告)号：US20210294367A1

公开(公告)日：2021-09-23

申请号：US17265361

申请日：2019-07-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Yuto YAKUBO ,  Hiroki INOUE

IPC: G05F1/56 ,  H03F3/45 ,  H01L29/786 ,  H03K3/356

Abstract: An output gain of a latch circuit is increased. The latch circuit includes a first circuit, a second circuit, and first to fourth transistors. The latch circuit includes a first input/output terminal and a second input/output terminal. The first circuit and the second circuit have a function of a current source. In the case where the third transistor is off and the fourth transistor is on, the latch circuit is supplied with a first input signal supplied to the first input/output terminal and a second input signal supplied to the second input/output terminal. In the case where the third transistor is on and the fourth transistor is off, an inverted signal of the first input signal is output to the first input/output terminal of the latch circuit, and an inverted signal of the second input signal is output to the second input/output terminal of the latch circuit. The first circuit and the second circuit increase the output gain of the latch circuit.

公开(公告)号：US20150349131A1

公开(公告)日：2015-12-03

申请号：US14723630

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Yoshiyuki KOBAYASHI ,  Yutaka SHIONOIRI ,  Yuto YAKUBO ,  Shuhei NAGATSUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  G05F3/262 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7782 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor.

Abstract translation: 提供占据小面积的半导体器件。 半导体器件包括电阻器。 电阻器包括晶体管。 当漏极电压高于晶体管的栅极电压和阈值电压之间的差时，漏极电压的0.1V变化的晶体管的漏极电流的增加率优选地高于或等于1％。 半导体器件具有基于电阻器的电阻产生电压的功能。

公开(公告)号：US20150325708A1

公开(公告)日：2015-11-12

申请号：US14704101

申请日：2015-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Suguru HONDO ,  Akihisa SHIMOMURA ,  Shunpei YAMAZAKI ,  Shuhei NAGATSUKA

IPC: H01L29/786 ,  H01L29/36 ,  H01L29/423 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/7869 ,  H01L29/78696

Abstract: A transistor capable of being driven at high operating frequency is provided. The transistor includes first to third oxide semiconductor layers, a gate insulating layer, a gate electrode layer, and a portion in which the first to third oxide semiconductor layers are sequentially stacked. Channel length is less than 100 nm, and cutoff frequency at a source-drain voltage of higher than or equal to 1 V and lower than or equal to 2 V is higher than 1 GHz. The gate insulating layer is in contact with a top surface of the third oxide semiconductor layer. The gate electrode layer partly overlaps with the portion with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a plurality of c-axis aligned crystal parts and a region in which the concentration of hydrogen measured by secondary ion mass spectrometry is lower than 2×1020 atoms/cm3.

Abstract translation: 提供能够以高工作频率驱动的晶体管。 晶体管包括第一至第三氧化物半导体层，栅极绝缘层，栅极电极层以及其中第一至第三氧化物半导体层顺序堆叠的部分。 通道长度小于100nm，源极 - 漏极电压高于或等于1V且低于或等于2V的截止频率高于1GHz。 栅极绝缘层与第三氧化物半导体层的顶表面接触。 栅极电极层与位于其间的栅极绝缘层的部分重叠。 第二氧化物半导体层包括多个c轴取向晶体部分和通过二次离子质谱法测量的氢浓度低于2×1020原子/ cm3的区域。

公开(公告)号：US20250040144A1

公开(公告)日：2025-01-30

申请号：US18780650

申请日：2024-07-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takanori MATSUZAKI ,  Yuto YAKUBO ,  Yuki OKAMOTO

IPC: H10B51/20 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H10B51/10 ,  H10B53/10 ,  H10B53/20

Abstract: A memory device with a novel structure. A first transistor includes a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer. A second transistor includes a second oxide semiconductor layer, the first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer. In a plan view, the first oxide semiconductor layer includes a region facing the first conductive layer with the first insulating layer therebetween and a region facing the second conductive layer with the second insulating layer therebetween. In a plan view, the second oxide semiconductor layer includes a region facing the fifth conductive layer with the third insulating layer therebetween and a region facing the sixth conductive layer with the fourth insulating layer therebetween. The first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer. The second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer. In a cross-sectional view, the third conductive layer includes a region overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer.

公开(公告)号：US20240221812A1

公开(公告)日：2024-07-04

申请号：US18409150

申请日：2024-01-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto YAKUBO ,  Takahiko ISHIZU

IPC: G11C11/405 ,  G11C11/4096 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: G11C11/405 ,  G11C11/4096 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H10B12/00

Abstract: A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.

公开(公告)号：US20230336006A1

公开(公告)日：2023-10-19

申请号：US18026910

申请日：2021-09-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidetomo KOBAYASHI ,  Yuto YAKUBO ,  Takayuki IKEDA

IPC: H02J7/00

CPC classification number: H02J7/0014 ,  H02J7/00302 ,  H02J7/00306

Abstract: A protection circuit and a control circuit of a secondary battery are provided, for example. A circuit with low power consumption is provided. A circuit with a high degree of integration is provided. The control circuit includes a first resistance circuit, a second resistance circuit, a comparator, and a memory circuit. One terminal of the first resistance circuit is electrically connected to a positive electrode of a secondary battery; the other terminal of the first resistance circuit is electrically connected to a first input terminal of the comparator and one terminal of the second resistance circuit; the memory circuit has a function of retaining first data; the control circuit has a function of generating a first signal and a second signal by using the first data, a function of adjusting the resistance of the first resistance circuit by supplying the first signal to the first resistance circuit, a function of adjusting the resistance of the second resistance circuit by supplying the second signal to the second resistance circuit, and a function of stopping one of charging and discharging of the secondary battery in accordance with output from the comparator; and the memory circuit includes a capacitor that includes a ferroelectric layer as a dielectric layer.

公开(公告)号：US20230178654A1

公开(公告)日：2023-06-08

申请号：US17924166

申请日：2021-05-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Takayuki IKEDA ,  Tatsuya ONUKI ,  Yuto YAKUBO

IPC: H01L29/786 ,  H01L23/29 ,  G06F7/544 ,  G06F21/34

CPC classification number: H01L29/7869 ,  H01L23/298 ,  G06F7/5443 ,  G06F21/34

Abstract: A semiconductor device that can be embedded in a living body is provided. The semiconductor device being embeddable in a living body includes a communication portion, a control portion, a memory portion, an arithmetic portion, and a sensor portion. The control portion has a function of controlling the communication portion, the arithmetic portion, and the memory portion. The memory portion has a function of retaining identification information. The arithmetic portion has a function of using first information and second information supplied from the sensor portion to generate third information. The control portion has a function of making the arithmetic portion perform arithmetic processing in response to a signal input through the communication portion. The control portion has a function of outputting, through the communication portion to the outside, one or both of the identification information and the third information, in response to a signal input through the communication portion. The arithmetic portion preferably includes a transistor including an oxide semiconductor in a channel formation region. The semiconductor device is preferably covered with a coating material.