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公开(公告)号：US09559727B1
公开(公告)日：2017-01-31
申请号：US14720566
申请日：2015-05-22
Applicant: SK hynix memory solutions inc.
Inventor： Naveen Kumar , Zheng Wu , Jason Bellorado
CPC classification number: H03M13/2975 , H03M13/152 , H03M13/2948 , H03M13/2963
Abstract: Row decoding is performed on row codewords in an array in order to produce a row decoded array that includes row decoded column codewords. Column decoding is performed on the row decoded column codewords in order to produce a row and column decoded array that includes row and column decoded row codewords and row and column decoded column codewords. The number of row and column decoded row codewords that are not in a row codebook is determined and the number of row and column decoded column codewords that are not in a column codebook are determined. If the number not in the row codebook equals 0 and the number not in the column codebook equals 1, at least a data portion of the row and column decoded array is output.
Abstract translation: 对阵列中的行码字执行行解码，以便产生包括行解码列码字的行解码数组。 对行解码列码字执行列解码，以便产生包括行和列解码的行码字以及行和列解码的列码字的行和列解码数组。 确定不在行码本中的行和列解码行码字的数量，并且确定不在列码本中的行和列解码列码字的数目。 如果不在行码本中的号码等于0，而不在列码本中的号码等于1，则至少输出行和列解码数组的数据部分。
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12.发明申请公开(公告)号：US20160217034A1
公开(公告)日：2016-07-28
申请号：US15092110
申请日：2016-04-06
Applicant: SK Hynix Memory Solutions Inc.
Inventor： Arunkumar Subramanian , Frederick K.H. Lee , Xiangyu Tang , Lingqi Zeng , Jason Bellorado
CPC classification number: G06F11/1068 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/02 , G11C29/52 , G11C2029/0411
Abstract: A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.
Abstract translation: 处理电荷约束位序列以获得与电荷约束位序列相关联的多个位错误的下限。 将下限与与纠错解码器相关联的纠错能力阈值进行比较。 在下限大于或等于纠错解码器阈值的情况下，预测出纠错解码失败。
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13.发明授权公开(公告)号：US09231619B2
公开(公告)日：2016-01-05
申请号：US14083186
申请日：2013-11-18
Applicant: SK hynix memory solutions inc.
Inventor： Lingqi Zeng , Qiuju Diao , Jason Bellorado
CPC classification number: H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/3723 , H03M13/658
Abstract: A first message, associated with going from one of a plurality of variable nodes to one of a plurality of check nodes is computed, wherein: (1) one or more connections between the plurality of variable nodes and the plurality of check nodes are specified by an LDPC parity check matrix and (2) a scaling constant is used to compute the first message. A second message, associated with going from one of the plurality of check nodes to one of a plurality of variable nodes, is computed, wherein the scaling constant is not used to compute the second message.
Abstract translation: 计算与从多个变量节点之一到多个校验节点之一相关联的第一消息，其中：（1）多个变量节点和多个校验节点之间的一个或多个连接由 LDPC奇偶校验矩阵和（2）缩放常数用于计算第一消息。 计算与从多个检查节点中的一个到多个可变节点之一相关联的第二消息，其中缩放常数不用于计算第二消息。
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公开(公告)号：US09124299B1
公开(公告)日：2015-09-01
申请号：US13852926
申请日：2013-03-28
Applicant: SK hynix memory solutions inc.
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: H03M13/41 , H03M5/145 , H03M13/3961 , H03M13/3994 , H03M13/4107 , H03M13/4169 , H03M13/42
Abstract: A set of branch metrics for a trellis associated with a Viterbi detector is generated. A set of path metrics associated with the trellis is generated based at least in part on the set of branch metrics, including by obtaining a pruned trellis by removing at least some portion of the trellis that is associated with an invalid bit sequence not permitted by a constrained code. A surviving path associated with the pruned trellis is selected based at least in part on the set of path metrics. A sequence of decisions associated with the surviving path is output.
Abstract translation: 生成与维特比检测器相关联的网格的一组分支度量。 至少部分地基于分支度量集合生成与网格相关联的一组路径度量，包括通过去除与不允许的无效比特序列相关联的网格的至少一部分来获得修剪的网格 约束代码。 至少部分地基于路径度量集来选择与修剪的网格相关联的幸存路径。 输出与存活路径相关联的一系列决定。
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公开(公告)号：US09026881B2
公开(公告)日：2015-05-05
申请号：US14146929
申请日：2014-01-03
Applicant: SK hynix memory solutions inc.
Inventor： Frederick K. H. Lee , Jason Bellorado , Zheng Wu , Marcus Marrow
CPC classification number: H03M13/1111 , G11B2020/185 , G11B2220/2508 , H03M13/612 , H03M13/6325 , H03M13/6343 , H04L1/0054 , H04L1/0057
Abstract: A codebook which includes a plurality of messages and a plurality of codewords, a specified codeword bit value, and a specified message bit value are obtained. The LLR for bit ci in a codeword is generated, including by: identifying, from the codebook, those codewords where bit ci has the specified codeword bit value; for a message which corresponds to one of the codewords where bit ci has the specified codeword bit value, identifying those bits which have the specified message bit value; and summing one or more LLR values which correspond to those bits, in the message which corresponds to one of the codewords where bit ci has the specified codeword bit value, which have the specified message bit value.
Abstract translation: 获得包括多个消息和多个码字的码本，指定的码字比特值和指定的消息比特值。 产生码字中的比特ci的LLR，包括：从码本中识别比特ci具有指定码字比特值的那些码字; 对于与其中位ci具有指定码字比特值的码字之一相对应的消息，识别具有指定消息比特值的那些比特; 并且在对应于具有指定消息比特值的比特ci具有指定码字比特值的码字中的一个的消息中对与这些比特相对应的一个或多个LLR值求和。
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Patent Agency Ranking
公开(公告)号：US08943386B1
公开(公告)日：2015-01-27
申请号：US13764515
申请日：2013-02-11
Applicant: SK hynix memory solutions inc.
Inventor： Frederick K. H. Lee , Jason Bellorado , Marcus Marrow
CPC classification number: G06F11/076 , G06F11/0727
Abstract: Bin identification information for a cell is generated. An estimation function is received where the estimation function trends toward a maximum soft read value at a first end and trends toward a minimum soft read value at a second end. A soft read value is determined for the cell based at least in part on the bin identification information and the estimation function.
Abstract translation: 生成小区的小区识别信息。 接收估计函数，其中估计函数趋向于在第一端处的最大软读取值，并且趋向于在第二端处的最小软读取值。 至少部分地基于所述箱标识信息和所述估计功能为所述小区确定软读取值。
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公开(公告)号：US20150006981A1
公开(公告)日：2015-01-01
申请号：US14298736
申请日：2014-06-06
Applicant: SK hynix memory solutions inc.
Inventor： Yu Kou , Lingqi Zeng , Jason Bellorado , Marcus Marrow
CPC classification number: G06F11/1076 , G06F11/08 , G06F11/1012 , G11C29/56004 , H03M13/015 , H03M13/1102 , H03M13/154
Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.
Abstract translation: 存储系统包括信道检测器，LDPC解码器和擦除块。 信道检测器被配置为接收对应于从存储器读取的数据的数据并输出LLR信号。 LDPC解码器被配置为接收LLR信号并将反馈信号输出到信道检测器。 擦除块被配置为擦除LLR信号和反馈信号中的至少一个的一部分。 一种测试方法包括产生与擦除模式对应的错误率函数。 该函数是多次LDPC迭代的函数。 该方法包括至少部分地基于错误率函数来确定测试参数，其中测试参数包括LDPC迭代的测试次数，通过错误率和擦除模式。 该方法包括使用测试参数测试存储设备。
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18.发明申请公开(公告)号：US20140223264A1
公开(公告)日：2014-08-07
申请号：US14083186
申请日：2013-11-18
Applicant: SK hynix memory solutions inc.
Inventor： Lingqi Zeng , Qiuju Diao , Jason Bellorado
IPC: G06F11/10
CPC classification number: H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/3723 , H03M13/658
Abstract: A first message, associated with going from one of a plurality of variable nodes to one of a plurality of check nodes is computed, wherein: (1) one or more connections between the plurality of variable nodes and the plurality of check nodes are specified by an LDPC parity check matrix and (2) a scaling constant is used to compute the first message. A second message, associated with going from one of the plurality of check nodes to one of a plurality of variable nodes, is computed, wherein the scaling constant is not used to compute the second message.
Abstract translation: 计算与从多个变量节点之一到多个校验节点之一相关联的第一消息，其中：（1）多个变量节点和多个校验节点之间的一个或多个连接由 LDPC奇偶校验矩阵和（2）缩放常数用于计算第一消息。 计算与从多个检查节点中的一个到多个可变节点之一相关联的第二消息，其中缩放常数不用于计算第二消息。
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公开(公告)号：US20140191887A1
公开(公告)日：2014-07-10
申请号：US14151656
申请日：2014-01-09
Applicant: SK HYNIX MEMORY SOLUTIONS INC.
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow
IPC: H03M7/46
Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).
Abstract translation: 对于n = 1，接收数组f（n）。 。 。 ，N，其中N是码字的长度。 对于n = 1，接收数组g（n）。 。 。 ，N，其中N是码字的长度。 使用阵列f（n）和阵列g（n）对输入数据进行编码以满足MTR约束和RLL约束。
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公开(公告)号：US20140013166A1
公开(公告)日：2014-01-09
申请号：US13902410
申请日：2013-05-24
Applicant: SK HYNIX MEMORY SOLUTIONS INC.
Inventor： Arunkumar Subramanian , Frederick K.H. Lee , Jason Bellorado , Xiangyu Tang , Lingqi Zeng
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/32 , G06F1/3225 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G11C7/00 , Y02D10/13 , Y02D10/14
Abstract: A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power.
Abstract translation: 获得回读比特序列和电荷约束信息。 至少部分地基于回读比特序列和电荷约束信息来确定与回读比特序列相关联的多个比特错误的下限。 比较与纠错解码器相关联的下限和纠错能力阈值。 在下限大于或等于纠错能力阈值的情况下，预测出纠错解码失败，并且响应于该预测，将部件配置为节省功率。
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