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公开(公告)号：US20240126452A1
公开(公告)日：2024-04-18
申请号：US18184547
申请日：2023-03-15
Applicant: SK hynix Inc.
Inventor： Do Hyun LEE , Tae Hoon KIM
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0673
Abstract: A storage device includes a memory device including a memory block including memory regions, and a controller configured to store read results of read operations by performing the read operations on the memory regions, to determine first reference values of the memory regions, respectively, based on the read results, to determine a second reference value of the memory block based on the first reference values, and to determine whether the memory block is a potential bad block based on the second reference value. Each of the read results is the number of error bits that are included in data that has been read from the memory region in a corresponding read operation, each of the first reference values is the smallest value among the read results of a plurality of read operations for a corresponding memory region, and the second reference value is the greatest value among the first reference values.
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公开(公告)号：US20220367567A1
公开(公告)日：2022-11-17
申请号：US17878678
申请日：2022-08-01
Applicant: SK hynix Inc.
Inventor： Si Jung YOO , Tae Hoon KIM , Hyung Dong LEE
Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
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公开(公告)号：US20210280781A1
公开(公告)日：2021-09-09
申请号：US16984688
申请日：2020-08-04
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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14.发明申请公开(公告)号：US20200027505A1
公开(公告)日：2020-01-23
申请号：US16296796
申请日：2019-03-08
Applicant: SK hynix Inc.
Inventor： Ki Won LEE , Seok Man HONG , Tae Hoon KIM , Hyung Dong LEE
IPC: G11C13/00
Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
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公开(公告)号：US20150127887A1
公开(公告)日：2015-05-07
申请号：US14266332
申请日：2014-04-30
Applicant: SK hynix Inc.
Inventor： Tae Hoon KIM , Joong Seob YANG
CPC classification number: G06F12/0246 , G06F1/30 , G11C5/143
Abstract: An operating method of a data storage system may include detecting a sudden power-off during a program operation on pages in a memory block, identifying a dummy program target page in the memory block when power is on after the sudden power-off, and performing the program operation on the dummy program target page using dummy data, and performing the program operation on pages in the memory block subsequent to the dummy program target page using normal data.
Abstract translation: 数据存储系统的操作方法可以包括在存储器块中的页面上的程序操作期间检测到突然断电，当在突然关断之后接通电源时识别存储器块中的虚拟程序目标页面，并执行 使用伪数据对虚拟程序目标页面上的程序操作，以及使用正常数据在虚拟程序目标页面之后的存储器块中的页面上执行程序操作。
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Patent Agency Ranking
16.发明申请METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME 有权减少半导体装置的输出数据噪声的方法和实现其的半导体装置公开(公告)号：US20150109041A1
公开(公告)日：2015-04-23
申请号：US14581357
申请日：2014-12-23
Applicant: SK hynix Inc.
Inventor： Sung Woo HAN , Ic Su OH , Jun Ho LEE , Boo Ho JUNG , Sun Ki CHO , Yang Hee KIM , Tae Hoon KIM
CPC classification number: H03K3/013 , G06F17/5022 , H03K5/12
Abstract: Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise.
Abstract translation: 提供了一种半导体装置，其包括多个输出缓冲器，其被配置为连接多个电源;以及数据噪声测量单元，被配置为将所述多个输出缓冲器中的所选输出缓冲器的输出数据固定为具有特定电平， 使用电容测量输出数据的噪声，并基于噪声控制多个输出缓冲器的转换速率。
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17.发明申请POWER METAL MESH AND SEMICONDUCTOR MEMORY DEVICE AND METHOD INCLUDING THE SAME 审中-公开功率金属网和半导体存储器件及其包括的方法公开(公告)号：US20140140016A1
公开(公告)日：2014-05-22
申请号：US13845568
申请日：2013-03-18
Applicant: SK HYNIX INC.
Inventor： Jun Ho LEE , Sung Woo HAN , Ic Su OH , Boo Ho JUNG , Sun Ki CHO , Yang Hee KIM , Tae Hoon KIM
CPC classification number: H03H7/0115 , G11C5/14 , H01L23/147 , H01L23/49827 , H01L23/5223 , H01L23/5227 , H01L23/5286 , H01L23/552 , H01L23/66 , H01L2223/6661 , H01L2924/0002 , H01L2924/00
Abstract: A power metal mesh and a semiconductor memory device including the same are provided. As the power metal mesh configured to reduce noise coupling generated between adjacent chips disposed on an interposer, a band stop filter unit including an inductor and a capacitor coupled in parallel is disposed between the adjacent chips to effectively reduce the noise coupling of a specific frequency band generated between the adjacent chips.
Abstract translation: 提供了一种功率金属网和包括其的半导体存储器件。 由于功率金属网被配置为减少在设置在插入器上的相邻芯片之间产生的噪声耦合，所以包括电感器和并联的电容器的带阻滤波器单元设置在相邻芯片之间，以有效地减小特定频带的噪声耦合 在相邻芯片之间产生。
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公开(公告)号：US20230170332A1
公开(公告)日：2023-06-01
申请号：US18103968
申请日：2023-01-31
Applicant: SK hynix Inc.
Inventor： Tae Hoon KIM
IPC: H01L25/065
CPC classification number: H01L25/0657 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/06593
Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.
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公开(公告)号：US20220115355A1
公开(公告)日：2022-04-14
申请号：US17203354
申请日：2021-03-16
Applicant: SK hynix Inc.
Inventor： Tae Hoon KIM
IPC: H01L25/065
Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.
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公开(公告)号：US20210066393A1
公开(公告)日：2021-03-04
申请号：US16860686
申请日：2020-04-28
Applicant: SK hynix Inc.
Inventor： Si Jung YOO , Tae Hoon KIM , Hyung Dong LEE
Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
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