公开(公告)号：US20150311110A1

公开(公告)日：2015-10-29

申请号：US14441473

申请日：2013-09-25

Applicant: SOITEC

Inventor： Christophe Gourdel ,  Oleg Kononchuk

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L21/7624 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/84

Abstract: The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment step is designed to partially dissolve the silicon dioxide layer, the heat treatment step being carried out in a non-oxidizing atmosphere and the pressure of the non-oxidizing atmosphere being lower than 0.1 bar.

Abstract translation: 本公开涉及一种用于制造多个绝缘体上半导体结构的方法，所述绝缘体是厚度小于50nm的二氧化硅层，每个结构包括置于二氧化硅层上的半导体层，制造 该方法包括对多个结构进行热处理的步骤，该热处理步骤设计成部分溶解二氧化硅层，该热处理步骤在非氧化性气氛中进行，非氧化性气氛的压力较低 超过0.1巴。

公开(公告)号：US12112976B2

公开(公告)日：2024-10-08

申请号：US17088426

申请日：2020-11-03

Applicant: Soitec

Inventor： Fabrice Letertre ,  Oleg Kononchuk

IPC: H01L21/762 ,  B32B7/12 ,  B32B9/04 ,  B32B38/00 ,  C30B29/68 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02 ,  H01L21/18 ,  H01L27/12 ,  H01L33/00

CPC classification number: H01L21/76251 ,  B32B7/12 ,  B32B9/04 ,  C30B29/68 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02002 ,  H01L21/185 ,  H01L27/1203 ,  B32B2457/14 ,  H01L33/0093 ,  Y10T156/1062 ,  Y10T428/24942

Abstract: The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.

公开(公告)号：US12002697B2

公开(公告)日：2024-06-04

申请号：US17042755

申请日：2019-03-22

Applicant: Soitec ,  Commissariat A L'Energie Atomique et aux Énergies Alternatives

Inventor： François Rieutord ,  Frédéric Mazen ,  Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed

IPC: H01L21/67 ,  G01N29/14 ,  G01N29/46 ,  H01L21/66

CPC classification number: H01L21/67288 ,  G01N29/14 ,  G01N29/46 ,  H01L21/67109 ,  H01L22/12 ,  G01N2291/2697

Abstract: A method for monitoring a heat treatment applied to a substrate comprising a weakened zone formed by implanting atomic species for splitting the substrate along the weakened zone, the substrate being arranged in a heating chamber, the method comprising recording sound in the interior or in the vicinity of the heating chamber and detecting, in the recording, a sound emitted by the substrate during the splitting thereof along the weakened zone. A device for the heat treatment of a batch of substrates comprises an annealing furnace comprising a heating chamber intended to receive the batch, at least one microphone configured to record sounds in the interior or in the vicinity of the heating chamber, and a processing system configured to detect, in an audio recording produced by the microphone, a sound emitted when a substrate splits.

公开(公告)号：US20240030060A1

公开(公告)日：2024-01-25

申请号：US17907243

申请日：2021-01-19

Applicant: Soitec ,  Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Inventor： Frédéric Mazen ,  François Rieutord ,  Marianne Coig ,  Helen Grampeix ,  Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed

IPC: H01L21/762 ,  H01L21/324

CPC classification number: H01L21/76254 ,  H01L21/3247

Abstract: A method for preparing a thin layer comprises a weakening step for forming a weakened zone in a central portion of a donor substrate, the weakened zone not extending into a peripheral portion of the donor substrate; a step of joining the main face of the donor substrate to a receiver substrate to form an assembly to be split; and a step of separating the assembly to be split, the separating step comprising a heat treatment resulting in the freeing of the thin layer from the donor substrate at the central portion thereof only. The method also comprises, after the separating step, a detaching step comprising the treating of the assembly to be split in order to detach the peripheral portion of the donor substrate from the receiver substrate.

公开(公告)号：US11367650B2

公开(公告)日：2022-06-21

申请号：US17109978

申请日：2020-12-02

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US20220158080A1

公开(公告)日：2022-05-19

申请号：US17649470

申请日：2022-01-31

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H01L41/312 ,  H01L41/08 ,  H03H9/02 ,  H03H9/00 ,  H03H3/02

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US11295950B2

公开(公告)日：2022-04-05

申请号：US16337206

申请日：2017-09-21

Applicant: Soitec

Inventor： David Sotta ,  Jean-Marc Bethoux ,  Oleg Kononchuk

IPC: H01L21/02

Abstract: A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.

公开(公告)号：US11127775B2

公开(公告)日：2021-09-21

申请号：US16477374

申请日：2018-01-10

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L27/12

Abstract: A substrate for a front-side-type image sensor includes, successively, a supporting semiconductor substrate, an electrically insulating layer, and a semiconductor layer, known as the active layer. The active layer is an epitaxial layer of silicon-germanium having a germanium content of less than 10%. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US20210143053A1

公开(公告)日：2021-05-13

申请号：US17109978

申请日：2020-12-02

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US10943815B2

公开(公告)日：2021-03-09

申请号：US16308602

申请日：2017-06-06

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms-cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms-cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.