公开(公告)号：US20170179137A1

公开(公告)日：2017-06-22

申请号：US15448626

申请日：2017-03-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： STEPHANE ALLEGRET-MARET ,  KANGGUO CHENG ,  BRUCE DORIS ,  PRASANNA KHARE ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065 ,  H01L29/06 ,  H01L27/12 ,  H01L21/02 ,  H01L29/165 ,  H01L21/311 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

公开(公告)号：US20170104082A1

公开(公告)日：2017-04-13

申请号：US14879968

申请日：2015-10-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： XIUYU CAI ,  CHUN-CHEN YEH ,  QING LIU ,  RUILONG XIE

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/51 ,  H01L21/768 ,  H01L29/78 ,  H01L21/311 ,  H01L21/283

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US20160379867A1

公开(公告)日：2016-12-29

申请号：US15262034

申请日：2016-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： BRUCE DORIS ,  HONG HE ,  QING LIU

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/225 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

公开(公告)号：US20160111338A1

公开(公告)日：2016-04-21

申请号：US14969393

申请日：2015-12-15

Applicant: STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  PRASANNA KHARE ,  QING LIU

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/823807 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract translation: 描述了用于在体基板上将诸如Si和SiGe的两种半导体材料类型的finFET共集成的方法。 用于finFET的鳍可以形成在第一半导体类型的外延层中，并被绝缘体覆盖。 可以去除一部分翅片以在绝缘体中形成空隙，并且可以通过在空隙中外延生长第二类型的半导体材料来填充空隙。 共同集成的finFET可以形成在相同的器件级。

公开(公告)号：US20160093639A1

公开(公告)日：2016-03-31

申请号：US14964648

申请日：2015-12-10

Applicant: STMICROELECTRONICS, INC.

Inventor： PIERRE MORIN ,  QING LIU ,  NICOLAS LOUBET

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/16 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

公开(公告)号：US20150303285A1

公开(公告)日：2015-10-22

申请号：US14748270

申请日：2015-06-24

Applicant: STMICROELECTRONICS, INC.

Inventor： QING LIU ,  PRASANNA KHARE ,  NICOLAS LOUBET

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract translation: 多鳍FINFET器件可以包括衬底和从衬底向上延伸并沿着衬底间隔开的多个半导体鳍片。 每个半导体鳍片可以具有相对的第一和第二端以及它们之间的中间部分，并且多个半导体鳍片的最外面的鳍片可以在其外表面上包括外延生长阻挡层。 FINFET还可以包括覆盖半导体鳍片的中间部分的至少一个栅极，在与其第一端相邻的半导体鳍片之间的多个凸起的外延半导体源极区域和在相邻的半导体鳍片之间的多个凸起的外延半导体漏极区域 其第二端。

公开(公告)号：US20150187881A1

公开(公告)日：2015-07-02

申请号：US14658975

申请日：2015-03-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： VEERARAGHAVAN S. BASKER ,  QING LIU ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

IPC: H01L29/165 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins.

Abstract translation: 具有鳍式晶体管的半导体器件包括形成在衬底上的多个基本上平行的半导体鳍片，以及横跨翅片的纵向轴线形成在翅片上的栅极结构。 源极和漏极区域形成在栅极结构的相对侧上并且通过在合并区域中的鳍片之间的外延生长的晶体材料与翅片合并。 在与栅极结构的两侧分开设置的区域中的翅片上形成界面层。 界面层形成在翅片的相对侧的顶部和至少一部分上。 接触线形成在界面层上，使得接触层在翅片上的界面层的顶表面和鳍片上的界面层的至少一部分侧面上形成。

公开(公告)号：US20150179453A1

公开(公告)日：2015-06-25

申请号：US14618498

申请日：2015-02-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  LAURENT GRENOUILLET ,  ALI KHAKIFIROOZ ,  YANNICK LE TIEC ,  QING LIU ,  MAUD VINET

IPC: H01L21/225 ,  H01L21/761 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。

公开(公告)号：US20150097244A1

公开(公告)日：2015-04-09

申请号：US14048244

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： QING LIU ,  Nicolas Loubet

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78603

Abstract: A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer.

Abstract translation: 制造半导体器件的方法包括在半导体晶片上形成掩埋氧化层。 掩埋氧化物层包括第一氧化物层，第一氧化物层上的氮化物层和氮化物层上的第二氧化物层。 在第二氧化物层上形成半导体层。 第一和第二沟道区形成在半导体层中。

公开(公告)号：US20140312423A1

公开(公告)日：2014-10-23

申请号：US13865795

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC.

Inventor： KANGGUO CHENG ,  BRUCE B. DORIS ,  ALI KHAKIFIROOZ ,  QING LIU ,  NICOLAS LOUBET ,  SCOTT LUNING

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。