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公开(公告)号：US09325490B2
公开(公告)日：2016-04-26
申请号：US14221162
申请日：2014-03-20
Applicant: STMicroelectronics International N.V.
Inventor： Anurag Tiwari , Kallol Chatterjee
CPC classification number: H04L7/027 , H03L7/087 , H03L7/22 , H04L7/033 , H04L7/0331 , H04L7/0332
Abstract: A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/−0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.
Abstract translation: 一种用于无参考CDR的电路和方法，通过使用用于频率检测的附加回路来提高效率和抖动容限。 这种改进的电路包括用于识别初始恢复的时钟信号是否比接收的数据流的实际比特率更快或更慢的频率检测器。 频率检测器提供+/- 0.5 UI的抖动容限，并且使用其他常规频率检测器的显着较少的组件。 组件数量较少，功耗明显降低。 在一个实施例中，FD仅使用四个触发器，两个与门和一个延迟电路。 在集成电路中使用更少的组件也减少了管芯空间。 具有高抖动容限和更少的组件是比传统的无参考CDR电路的改进。
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公开(公告)号：US09160336B2
公开(公告)日：2015-10-13
申请号：US13715721
申请日：2012-12-14
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Jain , Chittoor Parthasarathy , Kallol Chatterjee
IPC: G06F17/50 , H03K19/003
CPC classification number: H03K19/003 , G06F17/5045 , G06F2217/12 , Y02P90/265
Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.
Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。
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公开(公告)号：US08933737B1
公开(公告)日：2015-01-13
申请号：US14046041
申请日：2013-10-04
Inventor： Kallol Chatterjee , Nitin Agarwal , Junaid Yousuf , Nitin Gupta , Pierre Dautriche
CPC classification number: H03L7/095
Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.
Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。
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公开(公告)号：US11867572B2
公开(公告)日：2024-01-09
申请号：US17521123
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Pijush Kanti Panja , Kallol Chatterjee , Atul Dwivedi
IPC: H03K17/14 , G01K7/14 , G01K7/01 , H03K19/018 , H03M1/12
CPC classification number: G01K7/14 , G01K7/01 , H03K17/14 , H03K19/018 , H03M1/1245
Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ΔVbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ΔVbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.
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公开(公告)号：US11563436B2
公开(公告)日：2023-01-24
申请号：US17863708
申请日：2022-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
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Patent Agency Ranking
公开(公告)号：US11431342B2
公开(公告)日：2022-08-30
申请号：US17521210
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.
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17.发明授权公开(公告)号：US10090845B1
公开(公告)日：2018-10-02
申请号：US15471483
申请日：2017-03-28
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee
Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.
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公开(公告)号：US09461584B2
公开(公告)日：2016-10-04
申请号：US14576535
申请日：2014-12-19
Applicant: STMicroelectronics International N.V.
Inventor： Gauri Mittal , Kallol Chatterjee , Pallavi Muktesh , Nitin Jain , Pradeep Kumar Badrathwal
IPC: H03B5/36
CPC classification number: H03B5/364 , H03B5/366 , H03B2200/0012 , H03B2200/0038
Abstract: A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.
Abstract translation: 电路包括用于接收偏置电流并在输出节点产生振荡信号的振荡器电路。 电流差分电路从参考电流中减去输出节点处的电流以产生第一电流。 此外，电流镜像电路反射第一电流以产生偏置电流。 逆变器级耦合到输出节点，并且包括被配置为接收振荡信号并基于振荡信号产生第一和第二控制信号的输入分支。 至少一个放大支路接收第一和第二控制信号并放大第一和第二控制信号。 输出分支接收放大的第一和第二控制信号，并且基于放大的第一和第二控制信号产生振荡信号的放大版本。
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公开(公告)号：US09395730B2
公开(公告)日：2016-07-19
申请号：US13929549
申请日：2013-06-27
Applicant: STMicroelectronics International N.V.
Inventor： Saurabh Kumar Singh , Nitin Bansal , Kallol Chatterjee
Abstract: A method and apparatus are provided. The apparatus includes a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage. Device ratios of at least two of the plurality of devices are set such that the positive feedback loop is stable.
Abstract translation: 提供了一种方法和装置。 该装置包括多个装置，其形成用于将调节的输出电压朝向参考电压驱动的正反馈回路。 设置多个装置中的至少两个装置的装置比，使得正反馈环路是稳定的。
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20.发明授权Adaptive multi-stage slack borrowing for high performance error resilient computing 有权用于高性能错误弹性计算的自适应多级松弛借贷公开(公告)号：US08994416B2
公开(公告)日：2015-03-31
申请号：US14045642
申请日：2013-10-03
Inventor： Chittoor Parthasarathy , Nitin Chawla , Kallol Chatterjee , Pascal Urard
CPC classification number: H03K3/02 , H03K3/0375
Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.
Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。
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