公开(公告)号：US12087356B2

公开(公告)日：2024-09-10

申请号：US17849903

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/418

CPC classification number: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US10249363B2

公开(公告)日：2019-04-02

申请号：US16018610

申请日：2018-06-26

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C7/22 ,  G11C7/06 ,  G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16 ,  G11C7/10 ,  G11C8/16 ,  G11C11/413

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US20180301186A1

公开(公告)日：2018-10-18

申请号：US16018610

申请日：2018-06-26

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/419 ,  G06F1/06 ,  G06F13/16 ,  G11C11/418

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US09524242B2

公开(公告)日：2016-12-20

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US12237007B2

公开(公告)日：2025-02-25

申请号：US17852567

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori ,  Harsh Rawat ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

公开(公告)号：US12170120B2

公开(公告)日：2024-12-17

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh Chawla ,  Tanuj Kumar ,  Bhupender Singh ,  Harsh Rawat ,  Kedar Janardan Dhori ,  Manuj Ayodhyawasi ,  Nitin Chawla ,  Promod Kumar

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US12040013B2

公开(公告)日：2024-07-16

申请号：US17861384

申请日：2022-07-11

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar Verma ,  Harsh Rawat

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

公开(公告)号：US09311990B1

公开(公告)日：2016-04-12

申请号：US14573106

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Piyush Jain

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

Abstract: A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

Abstract translation: 伪双端口存储器包括具有读端口和写端口的一组双端口存储器单元，并且被配置为在多个寻址位置的每一个中存储数据字，以及一组具有读/写的单端口存储器单元 并且被配置为将数据字存储在多个寻址位置的每一个中。 有效数据存储单元被配置为存储对应于该组双端口存储器单元和该组单端口存储器单元的寻址位置的有效位。 控制电路被配置为访问该组双端口存储器单元和一组单端口存储器单元的寻址位置。 控制电路使用该组双端口存储单元的写入端口和一组单端口存储器单元的读/写端口执行同时写入操作，并更新有效数据存储单元中的对应的有效位，并且执行 在双端口存储单元集合和单端口存储单元集合的相同寻址位置处使用双端口存储单元组的读端口和单端口集合的读/写端口进行并行读操作 并且基于有效数据存储单元中的相应的有效位来确定哪个存储的数据字是有效的。

公开(公告)号：US09208040B2

公开(公告)日：2015-12-08

申请号：US14266067

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

IPC: G06F11/00 ,  G06F11/20

CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。

公开(公告)号：US20150317225A1

公开(公告)日：2015-11-05

申请号：US14266067

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

IPC: G06F11/20

CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。