公开(公告)号：US10024888B2

公开(公告)日：2018-07-17

申请号：US15618269

申请日：2017-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US09794054B2

公开(公告)日：2017-10-17

申请号：US14788721

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Tapas Nandy ,  Nitin Gupta

IPC: H04L7/00 ,  H04L5/00 ,  H04J3/06 ,  H04L7/033 ,  H04L1/00 ,  H04L7/027 ,  G06F1/10 ,  H04L7/02

CPC classification number: H04L7/0008 ,  G06F1/10 ,  H04J3/0685 ,  H04L1/0026 ,  H04L5/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L7/0337

Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

公开(公告)号：US09705665B2

公开(公告)日：2017-07-11

申请号：US15009696

申请日：2016-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Chowdhary ,  Vivek Uppal ,  Alok Kaushik ,  Sajal Kumar Mandal ,  Tapas Nandy ,  Sanjeev Chopra

IPC: H04L12/26 ,  H04L7/033 ,  H04L7/00 ,  H03L7/08 ,  H04L25/03 ,  H03L7/091

CPC classification number: H04L7/0087 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0338 ,  H04L25/03057 ,  H04L43/022

Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

公开(公告)号：US09647699B1

公开(公告)日：2017-05-09

申请号：US14984040

申请日：2015-12-30

Applicant: STMicroelectronics International N.V.

Inventor： Nitin Gupta ,  Tapas Nandy

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B1/04

CPC classification number: H04B1/04 ,  H03F3/24 ,  H04B2001/0408

Abstract: A power harvesting circuit for use in an open drain transmitter circuit is configured to generate two distinct harvested supply voltages at different voltage levels along with two distinct cascode voltages at different voltage levels. The harvested supply voltages are used to power circuitry in the transmitter circuit. The cascode voltages are used to bias cascode transistors in the open drain circuitry for different channels.

公开(公告)号：US20130127537A1

公开(公告)日：2013-05-23

申请号：US13735114

申请日：2013-01-07

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tapas Nandy ,  Surendra Kumar

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F1/0266 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45302 ,  H03F2203/45354 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45446 ,  H03F2203/45702

Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.

Abstract translation: 电路包括具有折叠共源共栅结构的差分放大器和一对共源共栅晶体管。 感测电路感测施加到差分放大器的差分输入信号的共模输入电压。 偏置发生器电路在折叠共源共栅结构中产生用于施加到该对共源共栅晶体管的偏置电压。 偏置发生器电路连接到感测电路的输出，使得产生的偏置电压具有取决于感测到的共模输入电压的值。 这种依赖性响应于共模输入电压的变化而稳定来自差分放大器的共模输出电压。