公开(公告)号：US20170194498A1

公开(公告)日：2017-07-06

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78684

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US20130095636A1

公开(公告)日：2013-04-18

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。

公开(公告)号：US10262898B2

公开(公告)日：2019-04-16

申请号：US15093416

申请日：2016-04-07

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L21/768 ,  H01L21/82 ,  H01L27/12 ,  H01L29/70 ,  H01L27/082 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US09759546B2

公开(公告)日：2017-09-12

申请号：US14442081

申请日：2013-09-19

Applicant: SOITEC ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Oleg Kononchuk ,  Didier Dutartre

IPC: G01B11/28 ,  G01B11/06 ,  G01B11/30 ,  H01L21/66 ,  G02B21/36

CPC classification number: G01B11/06 ,  G01B11/0633 ,  G01B11/30 ,  G02B21/361 ,  H01L22/12

Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to the given thickness difference, the thicknesses of the other layers being for their part identical in the two multilayer structures. The invention also relates to a measuring system implementing the method.

公开(公告)号：US09711550B2

公开(公告)日：2017-07-18

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146 ,  H01L31/11 ,  H01L31/18

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

公开(公告)号：US20160181382A1

公开(公告)日：2016-06-23

申请号：US14577656

申请日：2014-12-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  David Barge

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/41783 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.

Abstract translation: 一种用于形成晶体管的方法包括在绝缘体上硅（SOI）衬底的第一半导体层的顶表面上限定玛瑙结构。 门结构包括绝缘盖。 然后共形沉积第二半导体层。 沉积的第二半导体层包括在第一半导体层的表面上的外延部分和绝缘盖表面上的非晶部分。 然后使用选择性蚀刻除去非晶部分。 剩余的外延部分在晶体管栅极结构的任一侧上形成刻面凸起的源极 - 漏极结构。 用于小平面的倾斜表面的斜率取决于在保形沉积期间使用的工艺参数。

公开(公告)号：US08975154B2

公开(公告)日：2015-03-10

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。

公开(公告)号：US10658578B2

公开(公告)日：2020-05-19

申请号：US16168369

申请日：2018-10-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Morin ,  Didier Dutartre

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.

公开(公告)号：US10263110B2

公开(公告)日：2019-04-16

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/207 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US20180096844A1

公开(公告)日：2018-04-05

申请号：US15594763

申请日：2017-05-15

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Victorien Paredes-Saez

IPC: H01L21/02 ,  C30B25/10 ,  C30B25/14 ,  C30B25/02

CPC classification number: H01L21/02381 ,  C30B25/02 ,  C30B25/10 ,  C30B25/14 ,  C30B25/183 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02496 ,  H01L21/02532 ,  H01L21/0262

Abstract: A gas phase epitaxial deposition method deposits silicon, germanium, or silicon-germanium on a single-crystal semiconductor surface of a substrate. The substrate is placed in an epitaxy reactor swept by a carrier gas. The substrate temperature is controlled to increase to a first temperature value. Then, for a first time period, at least a first silicon precursor gas and/or a germanium precursor gas introduced. Then, the substrate temperature is decreased to a second temperature value. At the end of the first time period and during the temperature decrease, introduction of the first silicon precursor gas and/or the introduction of a second silicon precursor gas is maintained. The gases preferably have a partial pressure adapted to the formation of a silicon layer having a thickness smaller than 0.5 nm.