公开(公告)号：US11810898B2

公开(公告)日：2023-11-07

申请号：US18115122

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3512

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

公开(公告)号：US20230215841A1

公开(公告)日：2023-07-06

申请号：US18115122

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3192 ,  H01L24/32 ,  H01L24/16 ,  H01L23/49816 ,  H01L24/73 ,  H01L2924/3512 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

公开(公告)号：US20220130799A1

公开(公告)日：2022-04-28

申请号：US17382169

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

公开(公告)号：US20210111140A1

公开(公告)日：2021-04-15

申请号：US16912819

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Younglyong Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.

公开(公告)号：US12191238B2

公开(公告)日：2025-01-07

申请号：US18167369

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

Abstract: A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

公开(公告)号：US20240153898A1

公开(公告)日：2024-05-09

申请号：US18387656

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Minseung JI ,  Seungduk Baek ,  Aenee Jang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/06181 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565

Abstract: A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

公开(公告)号：US20240038728A1

公开(公告)日：2024-02-01

申请号：US18356289

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Wonil Lee

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H10B80/00 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/05 ,  H01L24/08 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2223/54426 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/32221 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, and having widths narrower than a width of the first semiconductor chip, and a molded layer on an upper surface of the first semiconductor chip. The first semiconductor chip includes first front-surface pads, a first back-surface insulating layer divided into a first region and a second region, first back-surface pads in the first region, dummy pads in the second region, the dummy pads respectively having an upper surface on which a metal oxide film is disposed, and a first through-electrode electrically connecting the first front-surface pads and the first back-surface pads to each other. The plurality of second semiconductor chips respectively includes second front-surface pads, second back-surface pads, and a second through-electrode electrically connecting the second front-surface pads and the second back-surface pads to each other.

公开(公告)号：US11862613B2

公开(公告)日：2024-01-02

申请号：US18117601

申请日：2023-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06544

Abstract: A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

公开(公告)号：US20230154819A1

公开(公告)日：2023-05-18

申请号：US18154919

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong KIM ,  Myungkee Chung ,  Aenee Jang

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/367 ,  H01L25/0652 ,  H01L23/3128

Abstract: A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

公开(公告)号：US20230086202A1

公开(公告)日：2023-03-23

申请号：US17839675

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Yoonsung Kim ,  Seungduk Baek ,  Yunrae Cho

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: A semiconductor package is provided. The semiconductor package includes, a base structure including a body, an upper pad on the body, and an upper insulating layer on a side surface of the upper pad, the base structure having a planar upper surface provided by the upper insulating layer and the upper pad; and a semiconductor chip on the planar upper surface of the base structure, and including a substrate, a wiring structure below the substrate, a low dielectric layer on a side surface of the wiring structure, a lower connection pad below the wiring structure, and a lower insulating layer on a side surface of the lower connection pad, the semiconductor chip having a planar lower surface provided by the lower insulating layer and the lower connection pad, a side surface provided by the lower insulating layer and the substrate, and a recess surface extending from one end of the side surface to one end of the planar lower surface, wherein the low dielectric layer is spaced apart from the recess surface of the semiconductor chip by the lower insulating layer.