公开(公告)号：US20170365604A1

公开(公告)日：2017-12-21

申请号：US15611893

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan SUH ,  Gi-gwan PARK ,  Dong-woo KIM ,  Dong-suk SHIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20170213913A1

公开(公告)日：2017-07-27

申请号：US15404697

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon LEE ,  Gi-gwan PARK ,  Tae-young KIM

IPC: H01L29/78 ,  H01L29/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/08 ,  H01L29/267

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2006 ,  H01L29/2206 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

公开(公告)号：US20170062211A1

公开(公告)日：2017-03-02

申请号：US15209093

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin LIM ,  Gi-gwan PARK ,  Sang-yub IE ,  Jong-han LEE ,  Jeong-hyuk YIM ,  Hye-ri HONG

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/02123 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/28185 ,  H01L21/3003 ,  H01L21/67207 ,  H01L29/66795

Abstract: Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.

Abstract translation: 提供制造半导体器件的方法。 所述方法可以包括形成从衬底突出的鳍状有源区，并形成覆盖鳍状有源区的顶表面和两个侧壁的栅极绝缘膜。 栅极绝缘膜可以包括高k电介质膜。 所述方法还可以包括在栅绝缘膜上形成含金属层，在含金属层上形成含有氢原子的硅封盖层，去除硅封盖层中所含的一部分氢原子，除去硅封盖 层和所述含金属层的至少一部分，并且在所述栅极绝缘膜上形成栅电极。 栅电极可以覆盖翅片型有源区的顶表面和两个侧壁。

公开(公告)号：US20240290888A1

公开(公告)日：2024-08-29

申请号：US18660809

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hoon LEE ,  Gi-gwan PARK ,  Tae-young KIM

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2006 ,  H01L29/2206 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

公开(公告)号：US20210305253A1

公开(公告)日：2021-09-30

申请号：US17345090

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan SUH ,  Gi-gwan PARK ,  Dong-woo KIM ,  Dong-suk SHIN

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US20200027986A1

公开(公告)日：2020-01-23

申请号：US16587227

申请日：2019-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun YOU ,  Gi-gwan PARK ,  Ki-il KIM

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US20190035934A1

公开(公告)日：2019-01-31

申请号：US16150795

申请日：2018-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-yup CHUNG ,  Myung-yoon UM ,  Dong-ho CHA ,  Jung-gun YOU ,  Gi-gwan PARK

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8238

CPC classification number: H01L29/7854 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846

Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

公开(公告)号：US20170221893A1

公开(公告)日：2017-08-03

申请号：US15390361

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk TAK ,  Tae-jong LEE ,  Gi-gwan PARK ,  Ji-myoung LEE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/02 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42376

Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.

公开(公告)号：US20170213905A1

公开(公告)日：2017-07-27

申请号：US15404673

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon LEE ,  Gi-gwan PARK ,  Tae-young KIM ,  Yi-young NA ,  Dae-hee KIM

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate; a gate insulating film covering a top surface and both side walls of the fin-shaped active region; a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film; one pair of insulating spacers on both side walls of the gate electrode; and a source region and a drain region on the substrate and respectively located on sides of the gate electrode. The source region and the drain region form a source/drain pair. The one pair of insulating spacers include protrusions that protrude from upper portions of the one pair of insulating spacers toward the gate electrode.

公开(公告)号：US20170062613A1

公开(公告)日：2017-03-02

申请号：US15223332

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-hyun Sung ,  Jung-gun YOU ,  Gi-gwan PARK ,  Ki-il KIM

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7854

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Abstract translation: 集成电路器件包括从衬底突出的鳍式有源区; 多个衬垫，其顺序地覆盖所述翅片型有源区的下侧壁; 所述器件隔离层覆盖所述翅片型有源区的下侧壁，所述多个衬垫位于所述器件隔离层和所述翅片型有源区之间; 以及栅极绝缘层，其延伸以覆盖鳍状有源区域的沟道区域，多个衬垫和器件隔离层，并且包括位于覆盖多个衬垫的栅极绝缘层的部分上的突起。