公开(公告)号：US20240143173A1

公开(公告)日：2024-05-02

申请号：US18408558

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20220367412A1

公开(公告)日：2022-11-17

申请号：US17873120

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng GU ,  Krishna MALLADI ,  Hongzhong ZHENG

IPC: H01L25/065 ,  H01L31/12 ,  H01L31/02 ,  H01L31/0232 ,  H01L25/18 ,  H04B10/80 ,  H04Q11/00 ,  G02F1/01

Abstract: According to one general aspect, an apparatus may include a memory circuit die configured to store a lookup table that converts first data to second data. The apparatus may also include a logic circuit die comprising combinatorial logic circuits configured to receive the second data. The apparatus may further include an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die.

公开(公告)号：US20220004321A1

公开(公告)日：2022-01-06

申请号：US17480061

申请日：2021-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan JIANG ,  Hongzhong ZHENG

IPC: G06F3/06 ,  G06F12/0831 ,  G06F9/46 ,  G06F12/1009

Abstract: A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

公开(公告)号：US20200184001A1

公开(公告)日：2020-06-11

申请号：US16388860

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng GU ,  Krishna MALLADI ,  Hongzhong ZHENG ,  Dimin NIU

IPC: G06F17/16 ,  G06F12/0877

Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

公开(公告)号：US20200167297A1

公开(公告)日：2020-05-28

申请号：US16777206

申请日：2020-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  lndong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20200065016A1

公开(公告)日：2020-02-27

申请号：US16180002

申请日：2018-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan JIANG ,  Qiang PENG ,  Andrew CHANG ,  Hongzhong ZHENG

IPC: G06F3/06 ,  G06F9/46

Abstract: A deduplication memory system includes a virtual memory space, a physical memory space and a memory manager. The memory manager generates a user data entry that is stored in the physical memory space. The user data entry represents a unique user data of a predetermined granularity appearing in the virtual memory space, and includes first and second portions. The first portion includes information relating to a number of duplication times the unique user data corresponding to the user data entry is duplicated in the virtual memory space, and the second portion includes a selected part of the unique user data from which the unique user data may be reconstructed. The first portion may include an index to an extended reference counter table or a special data pattern table if the number of duplication times of the unique user data is greater than or equal to a predetermined number.

公开(公告)号：US20200042477A1

公开(公告)日：2020-02-06

申请号：US16595452

申请日：2019-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

IPC: G06F13/28 ,  G06F9/445 ,  G06F9/48

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

公开(公告)号：US20190266049A1

公开(公告)日：2019-08-29

申请号：US16411122

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Hyun-Joong KIM ,  Won-Hyung SONG ,  Jangseok CHOI

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

公开(公告)号：US20180322007A1

公开(公告)日：2018-11-08

申请号：US15675679

申请日：2017-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F13/4239

Abstract: A hardware coding mechanism is described. The coding mechanism may include a first encoder to produce a first code using a base number of bits and a second encoder to produce a second code using a supplementary number of bits. The second code and the first code together may be stronger than the first code alone. A mode register stored in a storage may specify whether a switch to the second encoder is open or closed: the first coder is always used.

公开(公告)号：US20180210825A1

公开(公告)日：2018-07-26

申请号：US15461467

申请日：2017-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin GIM ,  Hongzhong ZHENG

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a host interface logic to receive a write command from a host and flash memory to store data. The SSD may also include an SSD controller, which may include storage for a just-in-time threshold and a tail latency threshold flash translation layer. The flash translation layer may invoke a just-in-time garbage collection strategy when the number of free pages on the SSD is less than the just-in-time threshold, and a tail latency-aware garbage collection strategy when the number of free pages is less than the tail latency threshold. The tail latency-aware garbage collection strategy may pair the write command with a garbage collection command.