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    Semiconductor package and method of fabricating the same
    16.
    发明授权
    Semiconductor package and method of fabricating the same 有权

    公开(公告)号：US12159858B2

    公开(公告)日：2024-12-03

    申请号：US17568361

    申请日：2022-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

    Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

    Semiconductor package and method of manufacturing the same
    17.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US12009328B2

    公开(公告)日：2024-06-11

    申请号：US17715479

    申请日：2022-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung

    IPC: H01L23/00

    CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05551

    Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

    SEMICONDUCTOR DEVICE
    18.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240032311A1

    公开(公告)日：2024-01-25

    申请号：US18180188

    申请日：2023-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

    IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

    CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27

    Abstract: A semiconductor device includes a peripheral circuit structure including peripheral circuits on a substrate and first bonding pads electrically connected to the peripheral circuits and a cell array structure including memory cells on a semiconductor layer and second bonding pads electrically connected to the memory cells and bonded to the first bonding pads. The cell array structure includes a stacked structure including insulating layers and electrodes, an external connection pad on a surface of the semiconductor layer, a dummy pattern at a same level as the semiconductor layer relative to the substrate, and a photosensitive insulating layer on the semiconductor layer and the dummy pattern. A first thickness of a portion of the photosensitive insulating layer vertically overlapping the external connection pad is greater than a second thickness of another portion of the photosensitive insulating layer vertically overlapping the dummy pattern.

    Semiconductor package with stack structure and method of manufacturing the semiconductor package
    19.
    发明授权
    Semiconductor package with stack structure and method of manufacturing the semiconductor package 有权

    公开(公告)号：US11488937B2

    公开(公告)日：2022-11-01

    申请号：US17218340

    申请日：2021-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo Chung ,  Myungkee Chung ,  Younglyong Kim

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/12

    Abstract: A semiconductor package includes a package substrate, a lower package structure on the package substrate that includes a mold substrate, a semiconductor chip in the mold substrate having chip pads exposed through the mold substrate, spacer chips in the mold substrate and spaced apart from the semiconductor chip, and a redistribution wiring layer on the mold substrate that has redistribution wirings electrically connected to the chip pads, first and second stack structures on the lower package structure spaced apart from each other, each of the first and second stack structures including stacked memory chips, and a molding member covering the lower package structure and the first and second stack structures, wherein the mold substrate includes a first covering portion covering side surfaces of the semiconductor chip and the spacer chips, and a second covering portion covering a lower surface of the semiconductor chip.

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